[llvm] [AMDGPU] Add intrinsics and MIs for ds_bvh_stack_* (PR #130007)

[Jay Foad via llvm-commits]

================
@@ -2714,19 +2714,20 @@ def int_amdgcn_ds_sub_gs_reg_rtn :
             [ImmArg<ArgIndex<1>>, IntrHasSideEffects, IntrWillReturn, IntrNoCallback, IntrNoFree],
             "", [SDNPMemOperand]>;
 
-class IntDSBVHStackRtn :
+class IntDSBVHStackRtn<LLVMType vdst, LLVMType data1> :
   Intrinsic<
-    [llvm_i32_ty, llvm_i32_ty], // %vdst, %addr
+    [vdst, llvm_i32_ty], // %vdst, %addr
     [
       llvm_i32_ty,   // %addr
       llvm_i32_ty,   // %data0
-      llvm_v4i32_ty, // %data1
+      data1,         // %data1
       llvm_i32_ty,   // %offset
     ],
     [ImmArg<ArgIndex<3>>, IntrWillReturn, IntrNoCallback, IntrNoFree]
   >;
 
-def int_amdgcn_ds_bvh_stack_rtn : IntDSBVHStackRtn;
+def int_amdgcn_ds_bvh_stack_rtn : IntDSBVHStackRtn</* vdst  = */ llvm_i32_ty,
+                                                   /* data1 = */ llvm_v4i32_ty>;
----------------
jayfoad wrote:

I think TableGen actually lets you write this as:
```suggestion
def int_amdgcn_ds_bvh_stack_rtn : IntDSBVHStackRtn<vdst = lvm_i32_ty,
                                                   data1 = llvm_v4i32_ty>;
```
Does that work?

https://github.com/llvm/llvm-project/pull/130007