[llvm] AMDGPU: Use generated checks in coalescer_distribute.ll (PR #131276)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/131276

>From 8d10c1466595faf33dcc930e866b269ec23ee332 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 14 Mar 2025 12:05:58 +0700
Subject: [PATCH] AMDGPU: Use generated checks in coalescer_distribute.ll

Also replace the undef with poison.
---
 .../CodeGen/AMDGPU/coalescer_distribute.ll    | 27 +++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll b/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
index 8f4d10411ed73..d07cc84865bea 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
+++ b/llvm/test/CodeGen/AMDGPU/coalescer_distribute.ll
@@ -1,8 +1,31 @@
-; RUN: llc -mtriple=amdgcn-- -verify-machineinstrs -o /dev/null %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck %s
+
 ; This testcase produces a situation with unused value numbers in subregister
 ; liveranges that get distributed by ConnectedVNInfoEqClasses.
 
 define amdgpu_kernel void @hoge(i1 %c0, i1 %c1, i1 %c2, i1 %c3, i1 %c4) {
+; CHECK-LABEL: hoge:
+; CHECK:       ; %bb.0: ; %bb
+; CHECK-NEXT:    s_load_dword s2, s[4:5], 0x9
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    s_bitcmp1_b32 s2, 0
+; CHECK-NEXT:    s_cselect_b64 s[0:1], -1, 0
+; CHECK-NEXT:    s_and_b64 s[4:5], s[0:1], vcc
+; CHECK-NEXT:    s_and_saveexec_b64 s[0:1], s[4:5]
+; CHECK-NEXT:    s_or_b64 exec, exec, s[0:1]
+; CHECK-NEXT:    s_bitcmp1_b32 s2, 24
+; CHECK-NEXT:    s_cselect_b64 s[0:1], -1, 0
+; CHECK-NEXT:    s_xor_b64 s[0:1], s[0:1], -1
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+; CHECK-NEXT:    v_cmp_ne_u32_e64 s[0:1], 1, v0
+; CHECK-NEXT:  .LBB0_1: ; %bb25
+; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    s_and_b64 vcc, exec, s[0:1]
+; CHECK-NEXT:    s_cbranch_vccnz .LBB0_1
+; CHECK-NEXT:  ; %bb.2: ; %bb30
+; CHECK-NEXT:    s_endpgm
 bb:
   %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
   br i1 %c0, label %bb2, label %bb23
@@ -11,7 +34,7 @@ bb2:
   br i1 %c1, label %bb6, label %bb8
 
 bb6:
-  %tmp7 = or i64 undef, undef
+  %tmp7 = or i64 poison, poison
   br label %bb8
 
 bb8: