[llvm] enable true16 for more test (PR #131212)

Brox Chen via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 13 13:46:27 PDT 2025


https://github.com/broxigarchen created https://github.com/llvm/llvm-project/pull/131212

None

>From d6118b50f3e6e7ba3612466b1a12eeeafb844cc7 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Thu, 13 Mar 2025 16:46:02 -0400
Subject: [PATCH] enable true16 for more test

---
 .../AMDGPU/llvm.amdgcn.image.sample.g16.ll    | 318 ++++++++++++------
 .../llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll  |  31 +-
 .../llvm.amdgcn.raw.tbuffer.load.d16.ll       |  46 ++-
 .../llvm.amdgcn.raw.tbuffer.store.d16.ll      |  78 +++--
 ...llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll |  25 +-
 ...lvm.amdgcn.struct.ptr.tbuffer.store.d16.ll |  34 +-
 .../llvm.amdgcn.struct.tbuffer.load.d16.ll    |  52 ++-
 .../llvm.amdgcn.struct.tbuffer.store.d16.ll   |  88 +++--
 8 files changed, 466 insertions(+), 206 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
index 449c4ebec889d..b6a8a1c2dea2d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
@@ -1,7 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
 
 define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
 ; GFX10-LABEL: sample_d_1d:
@@ -35,21 +37,37 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_d_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_d_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v4, v5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -66,21 +84,37 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_3d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v[6:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_3d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v[6:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_d_3d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_d_3d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v5, v[6:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_3d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_3d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_d_g16 v[0:3], [v0, v2, v3, v[5:8]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -118,21 +152,37 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX11-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_c_d_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_c_d_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_c_d_g16 v[0:3], [v0, v1, v3, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -170,21 +220,37 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_d_cl_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_d_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_d_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
-; GFX12-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_d_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v5, v6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_d_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v1.l
+; GFX12-TRUE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_d_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v0, v1, v0, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_d_cl_g16 v[0:3], [v0, v2, v4, v[5:6]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32(i32 15, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -224,21 +290,37 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_cl_2d:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX11-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_cl_2d:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_c_d_cl_2d:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
-; GFX12-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_c_d_cl_2d:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v5, v[6:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_cl_2d:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v4.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_cl_2d:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v3, v4, v3, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v1, v2, v1, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_c_d_cl_g16 v[0:3], [v0, v1, v3, v[5:7]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32(i32 15, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <4 x float> %v
@@ -257,21 +339,39 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_o_2darray_V1:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_c_d_o_2darray_V1:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v5, v5, v4, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v9, v5
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v4.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v9.l
+; GFX12-TRUE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_o_2darray_V1:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v5, v5, v4, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_c_d_o_g16 v0, [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f16.f32.f32(i32 4, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret float %v
@@ -290,21 +390,39 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
-; GFX11-LABEL: sample_c_d_o_2darray_V2:
-; GFX11:       ; %bb.0: ; %main_body
-; GFX11-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
-; GFX11-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    ; return to shader part epilog
+; GFX11-TRUE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX11-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX11-TRUE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    ; return to shader part epilog
 ;
-; GFX12-LABEL: sample_c_d_o_2darray_V2:
-; GFX12:       ; %bb.0: ; %main_body
-; GFX12-NEXT:    v_perm_b32 v5, v5, v4, 0x5040100
-; GFX12-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
-; GFX12-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
-; GFX12-NEXT:    s_wait_samplecnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX11-FAKE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX11-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v5, v4, 0x5040100
+; GFX11-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX11-FAKE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v4, v[6:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX12-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT:    v_mov_b32_e32 v9, v5
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v4.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v3.l
+; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v5.h, v9.l
+; GFX12-TRUE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12-TRUE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: sample_c_d_o_2darray_V2:
+; GFX12-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT:    v_perm_b32 v5, v5, v4, 0x5040100
+; GFX12-FAKE16-NEXT:    v_perm_b32 v2, v3, v2, 0x5040100
+; GFX12-FAKE16-NEXT:    image_sample_c_d_o_g16 v[0:1], [v0, v1, v2, v[5:8]], s[0:7], s[8:11] dmask:0x6 dim:SQ_RSRC_IMG_2D_ARRAY
+; GFX12-FAKE16-NEXT:    s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %v = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32 6, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
   ret <2 x float> %v
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
index 9c576039ff6ac..839892e38db49 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
@@ -3,7 +3,8 @@
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10-PACKED %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11-PACKED %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s
 
 define amdgpu_kernel void @tbuffer_store_d16_x(ptr addrspace(8) %rsrc, half %data) {
 ; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_x:
@@ -34,15 +35,25 @@ define amdgpu_kernel void @tbuffer_store_d16_x(ptr addrspace(8) %rsrc, half %dat
 ; GFX10-PACKED-NEXT:    tbuffer_store_format_d16_x v0, off, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED]
 ; GFX10-PACKED-NEXT:    s_endpgm
 ;
-; GFX11-PACKED-LABEL: tbuffer_store_d16_x:
-; GFX11-PACKED:       ; %bb.0: ; %main_body
-; GFX11-PACKED-NEXT:    s_clause 0x1
-; GFX11-PACKED-NEXT:    s_load_b32 s6, s[4:5], 0x34
-; GFX11-PACKED-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-PACKED-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-PACKED-NEXT:    v_mov_b32_e32 v0, s6
-; GFX11-PACKED-NEXT:    tbuffer_store_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
-; GFX11-PACKED-NEXT:    s_endpgm
+; GFX11-PACKED-TRUE16-LABEL: tbuffer_store_d16_x:
+; GFX11-PACKED-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-TRUE16-NEXT:    s_clause 0x1
+; GFX11-PACKED-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX11-PACKED-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-PACKED-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s6
+; GFX11-PACKED-TRUE16-NEXT:    tbuffer_store_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
+; GFX11-PACKED-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-PACKED-FAKE16-LABEL: tbuffer_store_d16_x:
+; GFX11-PACKED-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-FAKE16-NEXT:    s_clause 0x1
+; GFX11-PACKED-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX11-PACKED-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-PACKED-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v0, s6
+; GFX11-PACKED-FAKE16-NEXT:    tbuffer_store_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
+; GFX11-PACKED-FAKE16-NEXT:    s_endpgm
 main_body:
   call void @llvm.amdgcn.raw.ptr.tbuffer.store.f16(half %data, ptr addrspace(8) %rsrc, i32 0, i32 0, i32 33, i32 0)
   ret void
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
index bd7e9d2dfa32d..e08123608176c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
@@ -3,8 +3,10 @@
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX10-PACKED %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX12-PACKED %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX12-PACKED,GFX12-PACKED-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX12-PACKED,GFX12-PACKED-FAKE16 %s
 
 define amdgpu_ps half @tbuffer_load_d16_x(<4 x i32> inreg %rsrc) {
 ; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_x:
@@ -104,19 +106,33 @@ define amdgpu_ps half @tbuffer_load_d16_xyz(<4 x i32> inreg %rsrc) {
 ; GFX10-PACKED-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX10-PACKED-NEXT:    ; return to shader part epilog
 ;
-; GFX11-PACKED-LABEL: tbuffer_load_d16_xyz:
-; GFX11-PACKED:       ; %bb.0: ; %main_body
-; GFX11-PACKED-NEXT:    tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
-; GFX11-PACKED-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-PACKED-NEXT:    v_mov_b32_e32 v0, v1
-; GFX11-PACKED-NEXT:    ; return to shader part epilog
-;
-; GFX12-PACKED-LABEL: tbuffer_load_d16_xyz:
-; GFX12-PACKED:       ; %bb.0: ; %main_body
-; GFX12-PACKED-NEXT:    tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], null format:[BUF_FMT_32_FLOAT]
-; GFX12-PACKED-NEXT:    s_wait_loadcnt 0x0
-; GFX12-PACKED-NEXT:    v_mov_b32_e32 v0, v1
-; GFX12-PACKED-NEXT:    ; return to shader part epilog
+; GFX11-PACKED-TRUE16-LABEL: tbuffer_load_d16_xyz:
+; GFX11-PACKED-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-TRUE16-NEXT:    tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
+; GFX11-PACKED-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-PACKED-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.l
+; GFX11-PACKED-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-PACKED-FAKE16-LABEL: tbuffer_load_d16_xyz:
+; GFX11-PACKED-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-FAKE16-NEXT:    tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
+; GFX11-PACKED-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v0, v1
+; GFX11-PACKED-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-PACKED-TRUE16-LABEL: tbuffer_load_d16_xyz:
+; GFX12-PACKED-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-PACKED-TRUE16-NEXT:    tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], null format:[BUF_FMT_32_FLOAT]
+; GFX12-PACKED-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-PACKED-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.l
+; GFX12-PACKED-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-PACKED-FAKE16-LABEL: tbuffer_load_d16_xyz:
+; GFX12-PACKED-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-PACKED-FAKE16-NEXT:    tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], null format:[BUF_FMT_32_FLOAT]
+; GFX12-PACKED-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v0, v1
+; GFX12-PACKED-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %data = call <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0)
   %elt = extractelement <3 x half> %data, i32 2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
index cde2627008e27..c53c491c216e7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
@@ -3,9 +3,12 @@
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10-PACKED %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11-PACKED %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG %s
-; RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG,GFX12-PACKED-SDAG-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG,GFX12-PACKED-SDAG-FAKE16 %s
+; RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-TRUE16 %s
+; RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-FAKE16 %s
 
 define amdgpu_kernel void @tbuffer_store_d16_x(<4 x i32> %rsrc, half %data) {
 ; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_x:
@@ -36,25 +39,55 @@ define amdgpu_kernel void @tbuffer_store_d16_x(<4 x i32> %rsrc, half %data) {
 ; GFX10-PACKED-NEXT:    tbuffer_store_format_d16_x v0, off, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED]
 ; GFX10-PACKED-NEXT:    s_endpgm
 ;
-; GFX11-PACKED-LABEL: tbuffer_store_d16_x:
-; GFX11-PACKED:       ; %bb.0: ; %main_body
-; GFX11-PACKED-NEXT:    s_clause 0x1
-; GFX11-PACKED-NEXT:    s_load_b32 s6, s[4:5], 0x34
-; GFX11-PACKED-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-PACKED-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-PACKED-NEXT:    v_mov_b32_e32 v0, s6
-; GFX11-PACKED-NEXT:    tbuffer_store_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
-; GFX11-PACKED-NEXT:    s_endpgm
+; GFX11-PACKED-TRUE16-LABEL: tbuffer_store_d16_x:
+; GFX11-PACKED-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-TRUE16-NEXT:    s_clause 0x1
+; GFX11-PACKED-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX11-PACKED-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-PACKED-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s6
+; GFX11-PACKED-TRUE16-NEXT:    tbuffer_store_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
+; GFX11-PACKED-TRUE16-NEXT:    s_endpgm
 ;
-; GFX12-PACKED-LABEL: tbuffer_store_d16_x:
-; GFX12-PACKED:       ; %bb.0: ; %main_body
-; GFX12-PACKED-NEXT:    s_clause 0x1
-; GFX12-PACKED-NEXT:    s_load_b32 s6, s[4:5], 0x34
-; GFX12-PACKED-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-PACKED-NEXT:    s_wait_kmcnt 0x0
-; GFX12-PACKED-NEXT:    v_mov_b32_e32 v0, s6
-; GFX12-PACKED-NEXT:    tbuffer_store_d16_format_x v0, off, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM]
-; GFX12-PACKED-NEXT:    s_endpgm
+; GFX11-PACKED-FAKE16-LABEL: tbuffer_store_d16_x:
+; GFX11-PACKED-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-FAKE16-NEXT:    s_clause 0x1
+; GFX11-PACKED-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX11-PACKED-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-PACKED-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v0, s6
+; GFX11-PACKED-FAKE16-NEXT:    tbuffer_store_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
+; GFX11-PACKED-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-PACKED-SDAG-TRUE16-LABEL: tbuffer_store_d16_x:
+; GFX12-PACKED-SDAG-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    s_clause 0x1
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s6
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    tbuffer_store_d16_format_x v0, off, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM]
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-PACKED-SDAG-FAKE16-LABEL: tbuffer_store_d16_x:
+; GFX12-PACKED-SDAG-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    s_clause 0x1
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, s6
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    tbuffer_store_d16_format_x v0, off, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM]
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-PACKED-GISEL-LABEL: tbuffer_store_d16_x:
+; GFX12-PACKED-GISEL:       ; %bb.0: ; %main_body
+; GFX12-PACKED-GISEL-NEXT:    s_clause 0x1
+; GFX12-PACKED-GISEL-NEXT:    s_load_b32 s6, s[4:5], 0x34
+; GFX12-PACKED-GISEL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-PACKED-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-PACKED-GISEL-NEXT:    v_mov_b32_e32 v0, s6
+; GFX12-PACKED-GISEL-NEXT:    tbuffer_store_d16_format_x v0, off, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM]
+; GFX12-PACKED-GISEL-NEXT:    s_endpgm
 main_body:
   call void @llvm.amdgcn.raw.tbuffer.store.f16(half %data, <4 x i32> %rsrc, i32 0, i32 0, i32 33, i32 0)
   ret void
@@ -264,3 +297,6 @@ declare void @llvm.amdgcn.raw.tbuffer.store.f16(half, <4 x i32>, i32, i32, i32,
 declare void @llvm.amdgcn.raw.tbuffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32)
 declare void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half>, <4 x i32>, i32, i32, i32, i32)
 declare void @llvm.amdgcn.raw.tbuffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX12-PACKED-GISEL-FAKE16: {{.*}}
+; GFX12-PACKED-GISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
index 7f21fe8d238b8..98f3a4dd1c690 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
@@ -3,7 +3,8 @@
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX10-PACKED %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s
 
 define amdgpu_ps half @tbuffer_load_d16_x(ptr addrspace(8) inreg %rsrc) {
 ; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_x:
@@ -101,13 +102,21 @@ define amdgpu_ps half @tbuffer_load_d16_xyz(ptr addrspace(8) inreg %rsrc) {
 ; GFX10-PACKED-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX10-PACKED-NEXT:    ; return to shader part epilog
 ;
-; GFX11-PACKED-LABEL: tbuffer_load_d16_xyz:
-; GFX11-PACKED:       ; %bb.0: ; %main_body
-; GFX11-PACKED-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-PACKED-NEXT:    tbuffer_load_d16_format_xyz v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
-; GFX11-PACKED-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-PACKED-NEXT:    v_mov_b32_e32 v0, v1
-; GFX11-PACKED-NEXT:    ; return to shader part epilog
+; GFX11-PACKED-TRUE16-LABEL: tbuffer_load_d16_xyz:
+; GFX11-PACKED-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-PACKED-TRUE16-NEXT:    tbuffer_load_d16_format_xyz v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
+; GFX11-PACKED-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-PACKED-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.l
+; GFX11-PACKED-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-PACKED-FAKE16-LABEL: tbuffer_load_d16_xyz:
+; GFX11-PACKED-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-PACKED-FAKE16-NEXT:    tbuffer_load_d16_format_xyz v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
+; GFX11-PACKED-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v0, v1
+; GFX11-PACKED-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %data = call <3 x half> @llvm.amdgcn.struct.ptr.tbuffer.load.v3f16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
   %elt = extractelement <3 x half> %data, i32 2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
index 7e92f0d2c5973..530ace778cdc9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
@@ -3,7 +3,8 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-PACKED %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-PACKED %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s
 
 define amdgpu_kernel void @tbuffer_store_d16_x(ptr addrspace(8) %rsrc, half %data, i32 %vindex) {
 ; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_x:
@@ -37,16 +38,27 @@ define amdgpu_kernel void @tbuffer_store_d16_x(ptr addrspace(8) %rsrc, half %dat
 ; GFX10-PACKED-NEXT:    tbuffer_store_format_d16_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
 ; GFX10-PACKED-NEXT:    s_endpgm
 ;
-; GFX11-PACKED-LABEL: tbuffer_store_d16_x:
-; GFX11-PACKED:       ; %bb.0: ; %main_body
-; GFX11-PACKED-NEXT:    s_clause 0x1
-; GFX11-PACKED-NEXT:    s_load_b64 s[6:7], s[4:5], 0x10
-; GFX11-PACKED-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-PACKED-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-PACKED-NEXT:    v_mov_b32_e32 v0, s6
-; GFX11-PACKED-NEXT:    v_mov_b32_e32 v1, s7
-; GFX11-PACKED-NEXT:    tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
-; GFX11-PACKED-NEXT:    s_endpgm
+; GFX11-PACKED-TRUE16-LABEL: tbuffer_store_d16_x:
+; GFX11-PACKED-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-TRUE16-NEXT:    s_clause 0x1
+; GFX11-PACKED-TRUE16-NEXT:    s_load_b64 s[6:7], s[4:5], 0x10
+; GFX11-PACKED-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-PACKED-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s6
+; GFX11-PACKED-TRUE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX11-PACKED-TRUE16-NEXT:    tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
+; GFX11-PACKED-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-PACKED-FAKE16-LABEL: tbuffer_store_d16_x:
+; GFX11-PACKED-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-FAKE16-NEXT:    s_clause 0x1
+; GFX11-PACKED-FAKE16-NEXT:    s_load_b64 s[6:7], s[4:5], 0x10
+; GFX11-PACKED-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-PACKED-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v0, s6
+; GFX11-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX11-PACKED-FAKE16-NEXT:    tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
+; GFX11-PACKED-FAKE16-NEXT:    s_endpgm
 main_body:
   call void @llvm.amdgcn.struct.ptr.tbuffer.store.f16(half %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
   ret void
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
index f74b6fe7893ea..3328b40d81d5e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
@@ -3,8 +3,10 @@
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX10-PACKED %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED %s
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX12-PACKED %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX12-PACKED,GFX12-PACKED-TRUE16 %s
+; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX12-PACKED,GFX12-PACKED-FAKE16 %s
 
 define amdgpu_ps half @tbuffer_load_d16_x(<4 x i32> inreg %rsrc) {
 ; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_x:
@@ -117,21 +119,37 @@ define amdgpu_ps half @tbuffer_load_d16_xyz(<4 x i32> inreg %rsrc) {
 ; GFX10-PACKED-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX10-PACKED-NEXT:    ; return to shader part epilog
 ;
-; GFX11-PACKED-LABEL: tbuffer_load_d16_xyz:
-; GFX11-PACKED:       ; %bb.0: ; %main_body
-; GFX11-PACKED-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-PACKED-NEXT:    tbuffer_load_d16_format_xyz v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
-; GFX11-PACKED-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-PACKED-NEXT:    v_mov_b32_e32 v0, v1
-; GFX11-PACKED-NEXT:    ; return to shader part epilog
-;
-; GFX12-PACKED-LABEL: tbuffer_load_d16_xyz:
-; GFX12-PACKED:       ; %bb.0: ; %main_body
-; GFX12-PACKED-NEXT:    v_mov_b32_e32 v0, 0
-; GFX12-PACKED-NEXT:    tbuffer_load_d16_format_xyz v[0:1], v0, s[0:3], null format:[BUF_FMT_32_FLOAT] idxen
-; GFX12-PACKED-NEXT:    s_wait_loadcnt 0x0
-; GFX12-PACKED-NEXT:    v_mov_b32_e32 v0, v1
-; GFX12-PACKED-NEXT:    ; return to shader part epilog
+; GFX11-PACKED-TRUE16-LABEL: tbuffer_load_d16_xyz:
+; GFX11-PACKED-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-PACKED-TRUE16-NEXT:    tbuffer_load_d16_format_xyz v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
+; GFX11-PACKED-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-PACKED-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.l
+; GFX11-PACKED-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX11-PACKED-FAKE16-LABEL: tbuffer_load_d16_xyz:
+; GFX11-PACKED-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-PACKED-FAKE16-NEXT:    tbuffer_load_d16_format_xyz v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
+; GFX11-PACKED-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v0, v1
+; GFX11-PACKED-FAKE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-PACKED-TRUE16-LABEL: tbuffer_load_d16_xyz:
+; GFX12-PACKED-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-PACKED-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-PACKED-TRUE16-NEXT:    tbuffer_load_d16_format_xyz v[0:1], v0, s[0:3], null format:[BUF_FMT_32_FLOAT] idxen
+; GFX12-PACKED-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-PACKED-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.l
+; GFX12-PACKED-TRUE16-NEXT:    ; return to shader part epilog
+;
+; GFX12-PACKED-FAKE16-LABEL: tbuffer_load_d16_xyz:
+; GFX12-PACKED-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX12-PACKED-FAKE16-NEXT:    tbuffer_load_d16_format_xyz v[0:1], v0, s[0:3], null format:[BUF_FMT_32_FLOAT] idxen
+; GFX12-PACKED-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX12-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v0, v1
+; GFX12-PACKED-FAKE16-NEXT:    ; return to shader part epilog
 main_body:
   %data = call <3 x half> @llvm.amdgcn.struct.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
   %elt = extractelement <3 x half> %data, i32 2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
index 4a02973941ec5..bdb82999197d9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
@@ -3,10 +3,14 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=PREGFX10-PACKED %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-PACKED %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-PACKED %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG,GFX12-PACKED-SDAG-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG,GFX12-PACKED-SDAG-FAKE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG,GFX12-PACKED-SDAG-TRUE16 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG,GFX12-PACKED-SDAG-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-FAKE16 %s
 
 define amdgpu_kernel void @tbuffer_store_d16_x(<4 x i32> %rsrc, half %data, i32 %vindex) {
 ; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_x:
@@ -40,27 +44,60 @@ define amdgpu_kernel void @tbuffer_store_d16_x(<4 x i32> %rsrc, half %data, i32
 ; GFX10-PACKED-NEXT:    tbuffer_store_format_d16_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
 ; GFX10-PACKED-NEXT:    s_endpgm
 ;
-; GFX11-PACKED-LABEL: tbuffer_store_d16_x:
-; GFX11-PACKED:       ; %bb.0: ; %main_body
-; GFX11-PACKED-NEXT:    s_clause 0x1
-; GFX11-PACKED-NEXT:    s_load_b64 s[6:7], s[4:5], 0x10
-; GFX11-PACKED-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-PACKED-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-PACKED-NEXT:    v_mov_b32_e32 v0, s6
-; GFX11-PACKED-NEXT:    v_mov_b32_e32 v1, s7
-; GFX11-PACKED-NEXT:    tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
-; GFX11-PACKED-NEXT:    s_endpgm
+; GFX11-PACKED-TRUE16-LABEL: tbuffer_store_d16_x:
+; GFX11-PACKED-TRUE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-TRUE16-NEXT:    s_clause 0x1
+; GFX11-PACKED-TRUE16-NEXT:    s_load_b64 s[6:7], s[4:5], 0x10
+; GFX11-PACKED-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-PACKED-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s6
+; GFX11-PACKED-TRUE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX11-PACKED-TRUE16-NEXT:    tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
+; GFX11-PACKED-TRUE16-NEXT:    s_endpgm
 ;
-; GFX12-PACKED-LABEL: tbuffer_store_d16_x:
-; GFX12-PACKED:       ; %bb.0: ; %main_body
-; GFX12-PACKED-NEXT:    s_clause 0x1
-; GFX12-PACKED-NEXT:    s_load_b64 s[6:7], s[4:5], 0x10
-; GFX12-PACKED-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
-; GFX12-PACKED-NEXT:    s_wait_kmcnt 0x0
-; GFX12-PACKED-NEXT:    v_mov_b32_e32 v0, s6
-; GFX12-PACKED-NEXT:    v_mov_b32_e32 v1, s7
-; GFX12-PACKED-NEXT:    tbuffer_store_d16_format_x v0, v1, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM] idxen
-; GFX12-PACKED-NEXT:    s_endpgm
+; GFX11-PACKED-FAKE16-LABEL: tbuffer_store_d16_x:
+; GFX11-PACKED-FAKE16:       ; %bb.0: ; %main_body
+; GFX11-PACKED-FAKE16-NEXT:    s_clause 0x1
+; GFX11-PACKED-FAKE16-NEXT:    s_load_b64 s[6:7], s[4:5], 0x10
+; GFX11-PACKED-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX11-PACKED-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v0, s6
+; GFX11-PACKED-FAKE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX11-PACKED-FAKE16-NEXT:    tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
+; GFX11-PACKED-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-PACKED-SDAG-TRUE16-LABEL: tbuffer_store_d16_x:
+; GFX12-PACKED-SDAG-TRUE16:       ; %bb.0: ; %main_body
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    s_clause 0x1
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    s_load_b64 s[6:7], s[4:5], 0x10
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s6
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    tbuffer_store_d16_format_x v0, v1, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM] idxen
+; GFX12-PACKED-SDAG-TRUE16-NEXT:    s_endpgm
+;
+; GFX12-PACKED-SDAG-FAKE16-LABEL: tbuffer_store_d16_x:
+; GFX12-PACKED-SDAG-FAKE16:       ; %bb.0: ; %main_body
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    s_clause 0x1
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    s_load_b64 s[6:7], s[4:5], 0x10
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v0, s6
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    v_mov_b32_e32 v1, s7
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    tbuffer_store_d16_format_x v0, v1, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM] idxen
+; GFX12-PACKED-SDAG-FAKE16-NEXT:    s_endpgm
+;
+; GFX12-PACKED-GISEL-LABEL: tbuffer_store_d16_x:
+; GFX12-PACKED-GISEL:       ; %bb.0: ; %main_body
+; GFX12-PACKED-GISEL-NEXT:    s_clause 0x1
+; GFX12-PACKED-GISEL-NEXT:    s_load_b64 s[6:7], s[4:5], 0x10
+; GFX12-PACKED-GISEL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
+; GFX12-PACKED-GISEL-NEXT:    s_wait_kmcnt 0x0
+; GFX12-PACKED-GISEL-NEXT:    v_mov_b32_e32 v0, s6
+; GFX12-PACKED-GISEL-NEXT:    v_mov_b32_e32 v1, s7
+; GFX12-PACKED-GISEL-NEXT:    tbuffer_store_d16_format_x v0, v1, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM] idxen
+; GFX12-PACKED-GISEL-NEXT:    s_endpgm
 main_body:
   call void @llvm.amdgcn.struct.tbuffer.store.f16(half %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
   ret void
@@ -293,3 +330,6 @@ declare void @llvm.amdgcn.struct.tbuffer.store.f16(half, <4 x i32>, i32, i32, i3
 declare void @llvm.amdgcn.struct.tbuffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32, i32)
 declare void @llvm.amdgcn.struct.tbuffer.store.v3f16(<3 x half>, <4 x i32>, i32, i32, i32, i32, i32)
 declare void @llvm.amdgcn.struct.tbuffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32, i32)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX12-PACKED-GISEL-FAKE16: {{.*}}
+; GFX12-PACKED-GISEL-TRUE16: {{.*}}



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