[llvm] [AMDGPU] Fix a crash by skipping DBG instrs at start of sched region (PR #131167)

[Emma Pilkington via llvm-commits]

https://github.com/epilk created https://github.com/llvm/llvm-project/pull/131167

Fixes SWDEV-514946

>From 5ba3ed5d70ad5cf39804b4a5add6b8065799cf9b Mon Sep 17 00:00:00 2001
From: Emma Pilkington <Emma.Pilkington at amd.com>
Date: Thu, 13 Mar 2025 08:29:49 -0400
Subject: [PATCH] [AMDGPU] Fix a crash by skipping DBG instrs at start of sched
 region

Fixes SWDEV-514946
---
 llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp   |  2 ++
 .../AMDGPU/dbg-value-starts-sched-region.mir  | 30 +++++++++++++++++++
 2 files changed, 32 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir

diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index c277223de13ac..99a7dfe0ed20c 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -873,6 +873,8 @@ void GCNScheduleDAGMILive::computeBlockPressure(unsigned RegionIdx,
       Pressure[CurRegion] = RPTracker.moveMaxPressure();
       if (CurRegion-- == RegionIdx)
         break;
+      auto &Rgn = Regions[CurRegion];
+      NonDbgMI = &*skipDebugInstructionsForward(Rgn.first, Rgn.second);
     }
     RPTracker.advanceToNext();
     RPTracker.advanceBeforeNext();
diff --git a/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir b/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir
new file mode 100644
index 0000000000000..2fb9acf36bb5d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir
@@ -0,0 +1,30 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s
+
+# Verify we maintain live-ins even if the first instruction in sched region is
+# DBG_.
+
+---
+name:            sched
+tracksRegLiveness: true
+registers:
+- { id: 1, class: sgpr_32, preferred-register: '', flags: [  ] }
+- { id: 2, class: sgpr_32, preferred-register: '', flags: [  ] }
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: name: sched
+    ; CHECK: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
+    ; CHECK-NEXT: S_NOP 0
+    ; CHECK-NEXT: SCHED_BARRIER 0
+    ; CHECK-NEXT: DBG_VALUE
+    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:sgpr_32 = COPY [[DEF]]
+    ; CHECK-NEXT: S_NOP 0
+    ; CHECK-NEXT: S_ENDPGM 0
+    %1:sgpr_32 = IMPLICIT_DEF
+    S_NOP 0
+    SCHED_BARRIER 0
+    DBG_VALUE
+    dead %2:sgpr_32 = COPY %1
+    S_NOP 0
+    S_ENDPGM 0
+...