[llvm] 7661526 - [X86] combineConcatVectorOps - extend PSHUFD/LW/HW handling to support 512-bit types

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2025-03-13T14:52:17Z
New Revision: 7661526fdf74b589e16b4066d217c180c9bd936e

URL: https://github.com/llvm/llvm-project/commit/7661526fdf74b589e16b4066d217c180c9bd936e
DIFF: https://github.com/llvm/llvm-project/commit/7661526fdf74b589e16b4066d217c180c9bd936e.diff

LOG: [X86] combineConcatVectorOps - extend PSHUFD/LW/HW handling to support 512-bit types

VPSHUFD was already getting converted via the VPERMILPS AVX1 fallback

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 46a16fe3ac841..2f8bfe62277cd 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -58079,9 +58079,11 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
     case X86ISD::PSHUFHW:
     case X86ISD::PSHUFLW:
     case X86ISD::PSHUFD:
-      // TODO: 512-bit PSHUFD/LW/HW handling
-      if (!IsSplat && NumOps == 2 && VT.is256BitVector() &&
-          Subtarget.hasInt256() && llvm::all_of(Ops, [Op0](SDValue Op) {
+      if (!IsSplat &&
+          ((VT.is256BitVector() && Subtarget.hasInt256()) ||
+           (VT.is512BitVector() && Subtarget.useAVX512Regs() &&
+            (EltSizeInBits >= 32 || Subtarget.useBWIRegs()))) &&
+          llvm::all_of(Ops, [Op0](SDValue Op) {
             return Op.getOperand(1) == Op0.getOperand(1);
           })) {
         return DAG.getNode(Op0.getOpcode(), DL, VT,

diff  --git a/llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll b/llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
index 824147805d2a2..3cf2d42799381 100644
--- a/llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
+++ b/llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
@@ -265,23 +265,37 @@ define <32 x i16> @shuffle_v32i16_lshr_00_02_04_06_32_34_36_38_08_10_12_14_40_42
 }
 
 define <32 x i16> @shuffle_v32i16_concat_00_00_00_00_04_05_06_07_08_08_08_08_12_13_14_15_16_16_16_16_20_21_22_23_24_24_24_24_28_29_30_31(<16 x i16> %a0, <16 x i16> %a1) {
-; ALL-LABEL: shuffle_v32i16_concat_00_00_00_00_04_05_06_07_08_08_08_08_12_13_14_15_16_16_16_16_20_21_22_23_24_24_24_24_28_29_30_31:
-; ALL:       ## %bb.0:
-; ALL-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[0,0,0,0,4,5,6,7,8,8,8,8,12,13,14,15]
-; ALL-NEXT:    vpshuflw {{.*#+}} ymm1 = ymm1[0,0,0,0,4,5,6,7,8,8,8,8,12,13,14,15]
-; ALL-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; ALL-NEXT:    retq
+; KNL-LABEL: shuffle_v32i16_concat_00_00_00_00_04_05_06_07_08_08_08_08_12_13_14_15_16_16_16_16_20_21_22_23_24_24_24_24_28_29_30_31:
+; KNL:       ## %bb.0:
+; KNL-NEXT:    vpshuflw {{.*#+}} ymm0 = ymm0[0,0,0,0,4,5,6,7,8,8,8,8,12,13,14,15]
+; KNL-NEXT:    vpshuflw {{.*#+}} ymm1 = ymm1[0,0,0,0,4,5,6,7,8,8,8,8,12,13,14,15]
+; KNL-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; KNL-NEXT:    retq
+;
+; SKX-LABEL: shuffle_v32i16_concat_00_00_00_00_04_05_06_07_08_08_08_08_12_13_14_15_16_16_16_16_20_21_22_23_24_24_24_24_28_29_30_31:
+; SKX:       ## %bb.0:
+; SKX-NEXT:    ## kill: def $ymm0 killed $ymm0 def $zmm0
+; SKX-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; SKX-NEXT:    vpshuflw {{.*#+}} zmm0 = zmm0[0,0,0,0,4,5,6,7,8,8,8,8,12,13,14,15,16,16,16,16,20,21,22,23,24,24,24,24,28,29,30,31]
+; SKX-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a0, <16 x i16> %a1, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 5, i32 6, i32 7, i32 8, i32 8, i32 8, i32 8, i32 12, i32 13, i32 14, i32 15, i32 16, i32 16, i32 16, i32 16, i32 20, i32 21, i32 22, i32 23, i32 24, i32 24, i32 24, i32 24, i32 28, i32 29, i32 30, i32 31>
   ret <32 x i16> %shuffle
 }
 
 define <32 x i16> @shuffle_v32i16_concat_00_01_02_03_04_07_06_04_08_09_10_11_12_15_14_12_16_17_18_19_20_23_22_20_24_25_26_27_28_31_30_28(<16 x i16> %a0, <16 x i16> %a1) {
-; ALL-LABEL: shuffle_v32i16_concat_00_01_02_03_04_07_06_04_08_09_10_11_12_15_14_12_16_17_18_19_20_23_22_20_24_25_26_27_28_31_30_28:
-; ALL:       ## %bb.0:
-; ALL-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,7,6,4,8,9,10,11,12,15,14,12]
-; ALL-NEXT:    vpshufhw {{.*#+}} ymm1 = ymm1[0,1,2,3,4,7,6,4,8,9,10,11,12,15,14,12]
-; ALL-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
-; ALL-NEXT:    retq
+; KNL-LABEL: shuffle_v32i16_concat_00_01_02_03_04_07_06_04_08_09_10_11_12_15_14_12_16_17_18_19_20_23_22_20_24_25_26_27_28_31_30_28:
+; KNL:       ## %bb.0:
+; KNL-NEXT:    vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,7,6,4,8,9,10,11,12,15,14,12]
+; KNL-NEXT:    vpshufhw {{.*#+}} ymm1 = ymm1[0,1,2,3,4,7,6,4,8,9,10,11,12,15,14,12]
+; KNL-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; KNL-NEXT:    retq
+;
+; SKX-LABEL: shuffle_v32i16_concat_00_01_02_03_04_07_06_04_08_09_10_11_12_15_14_12_16_17_18_19_20_23_22_20_24_25_26_27_28_31_30_28:
+; SKX:       ## %bb.0:
+; SKX-NEXT:    ## kill: def $ymm0 killed $ymm0 def $zmm0
+; SKX-NEXT:    vinserti64x4 $1, %ymm1, %zmm0, %zmm0
+; SKX-NEXT:    vpshufhw {{.*#+}} zmm0 = zmm0[0,1,2,3,4,7,6,4,8,9,10,11,12,15,14,12,16,17,18,19,20,23,22,20,24,25,26,27,28,31,30,28]
+; SKX-NEXT:    retq
   %shuffle = shufflevector <16 x i16> %a0, <16 x i16> %a1, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 7, i32 6, i32 4, i32 8, i32 9, i32 10, i32 11, i32 12, i32 15, i32 14, i32 12, i32 16, i32 17, i32 18, i32 19, i32 20, i32 23, i32 22, i32 20, i32 24, i32 25, i32 26, i32 27, i32 28, i32 31, i32 30, i32 28>
   ret <32 x i16> %shuffle
 }