[llvm] [SLP] Make getSameOpcode support interchangeable instructions. (PR #127450)

[Han-Kuan Chen via llvm-commits]

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@@ -813,6 +813,302 @@ static std::optional<unsigned> getExtractIndex(Instruction *E) {
 }
 
 namespace {
+/// \returns true if \p Opcode is allowed as part of the main/alternate
+/// instruction for SLP vectorization.
+///
+/// Example of unsupported opcode is SDIV that can potentially cause UB if the
+/// "shuffled out" lane would result in division by zero.
+bool isValidForAlternation(unsigned Opcode) {
+  if (Instruction::isIntDivRem(Opcode))
+    return false;
+
+  return true;
+}
+
+/// Helper class that determines VL can use the same opcode.
+/// Alternate instruction is supported. In addition, it supports interchangeable
+/// instruction. An interchangeable instruction is an instruction that can be
+/// converted to another instruction with same semantics. For example, x << 1 is
+/// equal to x * 2. x * 1 is equal to x | 0.
+class BinOpSameOpcodeHelper {
+  using MaskType = std::uint_fast16_t;
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HanKuanChen wrote:

I care about the type is the fastest type for at least 16 bits. unsigned short only means it has at least 16 bits, but does not mean it is the fastest.

https://github.com/llvm/llvm-project/pull/127450