[llvm] [RISCV] Add combine for shadd family of instructions. (PR #130829)

[Nemanja Ivanovic via llvm-commits]

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@@ -14306,6 +14312,79 @@ static SDValue transformAddShlImm(SDNode *N, SelectionDAG &DAG,
   return DAG.getNode(ISD::SHL, DL, VT, SHADD, DAG.getConstant(Bits, DL, VT));
 }
 
+// Check if this SDValue is an add immediate that is fed by a shift of 1, 2, or 3.
+static bool checkAddiForShift(SDValue AddI, int64_t &AddConst, int64_t &ShlConst) {
+  // Based on testing it seems that performance degrades if the ADDI has
+  // more than 2 uses.
+  if (AddI->use_size() > 2)
+    return false;
+
+  auto *AddConstNode = dyn_cast<ConstantSDNode>(AddI->getOperand(1));
+  if (!AddConstNode)
+    return false;
+  AddConst = AddConstNode->getSExtValue();
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nemanjai wrote:

Minor nit: please defer actually setting `AddConst` and `ShlConst` to the end, just before `return true`. This way we're only modifying the output parameters if the query is successful.

https://github.com/llvm/llvm-project/pull/130829