[llvm] [RISCV] Add implicit operand {VL, VTYPE} in RISCVInsertVSETVLI when u… (PR #130733)
Hank Chang via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 12 22:25:00 PDT 2025
https://github.com/HankChang736 updated https://github.com/llvm/llvm-project/pull/130733
>From e834c56b5634c78580faa0a5435ae4aa0afa575a Mon Sep 17 00:00:00 2001
From: Hank Chang <hank.chang at sifive.com>
Date: Thu, 13 Mar 2025 12:35:01 +0800
Subject: [PATCH 1/3] Precommit: Add original test data for comparison
---
.../RISCV/rvv/vsetvl-cross-inline-asm.ll | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
new file mode 100644
index 0000000000000..2952bc3cb862b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
@@ -0,0 +1,39 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -verify-machineinstrs < %s | FileCheck %s
+
+define void @foo(<vscale x 8 x half> %0, <vscale x 8 x half> %1) {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: addi a0, a0, %lo(.LCPI0_0)
+; CHECK-NEXT: vlse32.v v12, (a0), zero
+; CHECK-NEXT: lui a0, 1
+; CHECK-NEXT: addiw a0, a0, -1096
+; CHECK-NEXT: vmv.v.v v16, v12
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: #APP
+; CHECK-NEXT: vfmadd.vv v16, v12, v12
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; CHECK-NEXT: #APP
+; CHECK-NEXT: vfmadd.vv v16, v12, v12
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: vse16.v v8, (zero)
+; CHECK-NEXT: ret
+entry:
+ %2 = tail call i64 @llvm.riscv.vsetvli.i64(i64 3000, i64 0, i64 0)
+ %3 = tail call <vscale x 8 x float> asm sideeffect "vfmadd.vv $0, $1, $2", "=^vr,^vr,^vr,0"(<vscale x 8 x float> zeroinitializer, <vscale x 8 x float> zeroinitializer, <vscale x 8 x float> zeroinitializer)
+ %4 = tail call <vscale x 8 x float> asm sideeffect "vfmadd.vv $0, $1, $2", "=^vr,^vr,^vr,0"(<vscale x 8 x float> zeroinitializer, <vscale x 8 x float> zeroinitializer, <vscale x 8 x float> %3)
+ tail call void @llvm.riscv.vse.nxv8f16.i64(<vscale x 8 x half> %0, ptr null, i64 %2)
+ ret void
+}
+
+; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
+declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #0
+
+; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
+declare void @llvm.riscv.vse.nxv8f16.i64(<vscale x 8 x half>, ptr nocapture, i64) #1
+
+attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
>From 7526224170acffaf06b9e66670dea5040d8e2722 Mon Sep 17 00:00:00 2001
From: Hank Chang <hank.chang at sifive.com>
Date: Mon, 10 Mar 2025 12:27:22 +0800
Subject: [PATCH 2/3] [RISCV] Add implicit operand {VL, VTYPE} in
RISCVInsertVSETVLI when using inline assembly.
---
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 7 +++++++
llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll | 9 +++++++++
2 files changed, 16 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 7433603daff85..2247610c21ffb 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1531,6 +1531,13 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
/*isImp*/ true));
}
+ if (MI.isInlineAsm()) {
+ MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ true,
+ /*isImp*/ true));
+ MI.addOperand(MachineOperand::CreateReg(RISCV::VTYPE, /*isDef*/ true,
+ /*isImp*/ true));
+ }
+
if (MI.isCall() || MI.isInlineAsm() ||
MI.modifiesRegister(RISCV::VL, /*TRI=*/nullptr) ||
MI.modifiesRegister(RISCV::VTYPE, /*TRI=*/nullptr))
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
index 2952bc3cb862b..39986abe0abdb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
@@ -11,6 +11,11 @@ define void @foo(<vscale x 8 x half> %0, <vscale x 8 x half> %1) {
; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: addiw a0, a0, -1096
; CHECK-NEXT: vmv.v.v v16, v12
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: lui a0, 1
+; CHECK-NEXT: addiw a0, a0, -1096
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: #APP
; CHECK-NEXT: vfmadd.vv v16, v12, v12
@@ -19,6 +24,10 @@ define void @foo(<vscale x 8 x half> %0, <vscale x 8 x half> %1) {
; CHECK-NEXT: #APP
; CHECK-NEXT: vfmadd.vv v16, v12, v12
; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: #APP
+; CHECK-NEXT: vfmadd.vv v16, v12, v12
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vse16.v v8, (zero)
; CHECK-NEXT: ret
entry:
>From 066c6b603d66b498b648b1cb0de643fa16e62015 Mon Sep 17 00:00:00 2001
From: Hank Chang <hank.chang at sifive.com>
Date: Thu, 13 Mar 2025 12:31:06 +0800
Subject: [PATCH 3/3] Address Luke's comment
---
.../RISCV/rvv/vsetvl-cross-inline-asm.ll | 20 -------------------
1 file changed, 20 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
index 39986abe0abdb..ea42c3bbc3f47 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
@@ -4,13 +4,6 @@
define void @foo(<vscale x 8 x half> %0, <vscale x 8 x half> %1) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
-; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; CHECK-NEXT: addi a0, a0, %lo(.LCPI0_0)
-; CHECK-NEXT: vlse32.v v12, (a0), zero
-; CHECK-NEXT: lui a0, 1
-; CHECK-NEXT: addiw a0, a0, -1096
-; CHECK-NEXT: vmv.v.v v16, v12
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: lui a0, 1
@@ -20,10 +13,6 @@ define void @foo(<vscale x 8 x half> %0, <vscale x 8 x half> %1) {
; CHECK-NEXT: #APP
; CHECK-NEXT: vfmadd.vv v16, v12, v12
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: #APP
-; CHECK-NEXT: vfmadd.vv v16, v12, v12
-; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: vfmadd.vv v16, v12, v12
; CHECK-NEXT: #NO_APP
@@ -37,12 +26,3 @@ entry:
tail call void @llvm.riscv.vse.nxv8f16.i64(<vscale x 8 x half> %0, ptr null, i64 %2)
ret void
}
-
-; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
-declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #0
-
-; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
-declare void @llvm.riscv.vse.nxv8f16.i64(<vscale x 8 x half>, ptr nocapture, i64) #1
-
-attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) }
-attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
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