[llvm] [ARM]Adjust cost of muls in SMLAL patterns (PR #122713)

[Nashe Mncube via llvm-commits]

nasherm wrote:

Update:
After revisiting this I narrowed down the cause of our regressions. Changes to the SLPVectorizer caused a regression
in some benchmarks which targeted cores that support
both DSP and MVE instructions. The particular regression
has been reduced to a case where MUL instructions that
are part of a chain of instructions that can be replaced
with DSP SMLAL may also be vectorized. The generated
code ends up being an inefficient combination of both scalar
and vector ops rather than leaning to one or the other.
By reducing the cost of these MUL instructions in these
patterns we recover lost performance.

https://github.com/llvm/llvm-project/pull/122713