[llvm] AMDGPU: Replace insertelement poison with insertelement undef (PR #130896)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 12 02:15:27 PDT 2025
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/130896
>From e980e7c880682dd9905c12222fb06b7e278ae03b Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Wed, 12 Mar 2025 12:25:43 +0700
Subject: [PATCH] AMDGPU: Replace insertelement poison with insertelement undef
This is the bulk update with perl, with cases which require additional
update left for later.
---
.../AMDGPU/GlobalISel/cvt_f32_ubyte.ll | 2 +-
.../AMDGPU/GlobalISel/function-returns.ll | 6 +-
.../AMDGPU/GlobalISel/lds-misaligned-bug.ll | 12 +-
.../GlobalISel/llvm.amdgcn.intersect_ray.ll | 36 ++--
.../CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll | 2 +-
.../CodeGen/AMDGPU/GlobalISel/srem.i64.ll | 2 +-
.../CodeGen/AMDGPU/GlobalISel/udiv.i64.ll | 2 +-
.../CodeGen/AMDGPU/GlobalISel/urem.i64.ll | 2 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll | 4 +-
llvm/test/CodeGen/AMDGPU/add3.ll | 4 +-
.../AMDGPU/amdpal_scratch_mergedshader.ll | 2 +-
.../CodeGen/AMDGPU/any_extend_vector_inreg.ll | 2 +-
llvm/test/CodeGen/AMDGPU/anyext.ll | 2 +-
llvm/test/CodeGen/AMDGPU/bf16-conversions.ll | 4 +-
llvm/test/CodeGen/AMDGPU/bfi_nested.ll | 2 +-
llvm/test/CodeGen/AMDGPU/big_alu.ll | 180 +++++++++---------
llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll | 4 +-
.../CodeGen/AMDGPU/bug-v4f64-subvector.ll | 16 +-
.../AMDGPU/build-vector-insert-elt-infloop.ll | 2 +-
.../build-vector-packed-partial-undef.ll | 24 +--
llvm/test/CodeGen/AMDGPU/build_vector-r600.ll | 2 +-
llvm/test/CodeGen/AMDGPU/build_vector.ll | 2 +-
llvm/test/CodeGen/AMDGPU/bypass-div.ll | 4 +-
llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll | 30 +--
llvm/test/CodeGen/AMDGPU/coalescer_remat.ll | 4 +-
llvm/test/CodeGen/AMDGPU/collapse-endcf.ll | 2 +-
llvm/test/CodeGen/AMDGPU/complex-folding.ll | 2 +-
llvm/test/CodeGen/AMDGPU/cube.ll | 2 +-
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 2 +-
.../AMDGPU/dagcomb-shuffle-vecextend-non2.ll | 4 +-
.../dagcombiner-bug-illegal-vec4-int-to-fp.ll | 4 +-
.../dead-machine-elim-after-dead-lane.ll | 2 +-
llvm/test/CodeGen/AMDGPU/debug-value.ll | 8 +-
llvm/test/CodeGen/AMDGPU/debug-value2.ll | 18 +-
.../CodeGen/AMDGPU/divergence-driven-abs.ll | 8 +-
.../AMDGPU/divergence-driven-buildvector.ll | 32 ++--
.../AMDGPU/ds-combine-with-dependence.ll | 8 +-
llvm/test/CodeGen/AMDGPU/ds_read2.ll | 10 +-
llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll | 4 +-
llvm/test/CodeGen/AMDGPU/ds_write2.ll | 2 +-
.../AMDGPU/extract-subvector-equal-length.ll | 2 +-
...extract-vector-elt-build-vector-combine.ll | 6 +-
.../AMDGPU/fcanonicalize-elimination.ll | 2 +-
llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll | 8 +-
llvm/test/CodeGen/AMDGPU/floor.ll | 2 +-
llvm/test/CodeGen/AMDGPU/fmac.sdwa.ll | 6 +-
...formation-fmul-distribute-denormal-mode.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fmad.ll | 2 +-
llvm/test/CodeGen/AMDGPU/fmax.ll | 2 +-
llvm/test/CodeGen/AMDGPU/fmin.ll | 2 +-
llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fneg-combines.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll | 4 +-
.../CodeGen/AMDGPU/frame-index-elimination.ll | 2 +-
llvm/test/CodeGen/AMDGPU/function-returns.ll | 4 +-
.../AMDGPU/global-load-saddr-to-vaddr.ll | 2 +-
llvm/test/CodeGen/AMDGPU/global-saddr-load.ll | 8 +-
llvm/test/CodeGen/AMDGPU/image-schedule.ll | 2 +-
.../CodeGen/AMDGPU/indirect-addressing-si.ll | 8 +-
llvm/test/CodeGen/AMDGPU/input-mods.r600.ll | 2 +-
.../CodeGen/AMDGPU/insert_vector_dynelt.ll | 2 +-
llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll | 2 +-
llvm/test/CodeGen/AMDGPU/jump-address.ll | 2 +-
llvm/test/CodeGen/AMDGPU/kcache-fold.ll | 4 +-
llvm/test/CodeGen/AMDGPU/lds-bounds.ll | 8 +-
llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll | 4 +-
.../test/CodeGen/AMDGPU/lds-misaligned-bug.ll | 24 +--
.../CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll | 8 +-
.../llvm.amdgcn.image.sample.d16.dim.ll | 6 +-
.../AMDGPU/llvm.amdgcn.image.sample.dim.ll | 16 +-
.../AMDGPU/llvm.amdgcn.intersect_ray.ll | 36 ++--
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.pow.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.r600.cube.ll | 4 +-
llvm/test/CodeGen/AMDGPU/load-hi16.ll | 100 +++++-----
llvm/test/CodeGen/AMDGPU/load-input-fold.ll | 6 +-
llvm/test/CodeGen/AMDGPU/load-lo16.ll | 18 +-
.../loop-live-out-copy-undef-subrange.ll | 2 +-
.../lower-work-group-id-intrinsics-hsa.ll | 2 +-
.../lower-work-group-id-intrinsics-pal.ll | 2 +-
llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll | 12 +-
llvm/test/CodeGen/AMDGPU/mad_uint24.ll | 2 +-
llvm/test/CodeGen/AMDGPU/max-literals.ll | 8 +-
llvm/test/CodeGen/AMDGPU/memory_clause.ll | 4 +-
llvm/test/CodeGen/AMDGPU/merge-store-crash.ll | 6 +-
llvm/test/CodeGen/AMDGPU/mfma-loop.ll | 6 +-
llvm/test/CodeGen/AMDGPU/nsa-reassign.ll | 8 +-
llvm/test/CodeGen/AMDGPU/operand-folding.ll | 4 +-
llvm/test/CodeGen/AMDGPU/pack.v2f16.ll | 20 +-
llvm/test/CodeGen/AMDGPU/pack.v2i16.ll | 18 +-
llvm/test/CodeGen/AMDGPU/packed-fp32.ll | 24 +--
llvm/test/CodeGen/AMDGPU/packed-op-sel.ll | 22 +--
llvm/test/CodeGen/AMDGPU/predicate-dp4.ll | 2 +-
.../CodeGen/AMDGPU/ps-shader-arg-count.ll | 56 +++---
llvm/test/CodeGen/AMDGPU/pv-packing.ll | 4 +-
llvm/test/CodeGen/AMDGPU/pv.ll | 16 +-
llvm/test/CodeGen/AMDGPU/r600-encoding.ll | 2 +-
llvm/test/CodeGen/AMDGPU/r600-export-fix.ll | 16 +-
...nite-loop-bug-while-reorganizing-vector.ll | 8 +-
llvm/test/CodeGen/AMDGPU/r600cfg.ll | 10 +-
llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll | 2 +-
llvm/test/CodeGen/AMDGPU/rv7x0_count3.ll | 2 +-
llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll | 10 +-
.../AMDGPU/schedule-fs-loop-nested-if.ll | 2 +-
.../CodeGen/AMDGPU/schedule-fs-loop-nested.ll | 2 +-
llvm/test/CodeGen/AMDGPU/schedule-fs-loop.ll | 2 +-
llvm/test/CodeGen/AMDGPU/schedule-if-2.ll | 2 +-
llvm/test/CodeGen/AMDGPU/schedule-if.ll | 2 +-
.../schedule-vs-if-nested-loop-failure.ll | 4 +-
.../AMDGPU/schedule-vs-if-nested-loop.ll | 4 +-
.../AMDGPU/scheduler-subrange-crash.ll | 14 +-
llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll | 8 +-
.../AMDGPU/sgpr-copy-duplicate-operand.ll | 2 +-
llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll | 4 +-
llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll | 14 +-
.../AMDGPU/si-triv-disjoint-mem-access.ll | 2 +-
llvm/test/CodeGen/AMDGPU/si-vector-hang.ll | 8 +-
.../skip-promote-alloca-vector-users.ll | 4 +-
llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll | 4 +-
llvm/test/CodeGen/AMDGPU/sminmax.ll | 16 +-
llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll | 16 +-
llvm/test/CodeGen/AMDGPU/smrd.ll | 6 +-
.../CodeGen/AMDGPU/spill-vector-superclass.ll | 2 +-
.../CodeGen/AMDGPU/split-scalar-i64-add.ll | 10 +-
.../AMDGPU/splitkit-getsubrangeformask.ll | 32 ++--
llvm/test/CodeGen/AMDGPU/sram-ecc-default.ll | 2 +-
.../CodeGen/AMDGPU/subreg-coalescer-crash.ll | 14 +-
.../AMDGPU/subreg-coalescer-undef-use.ll | 4 +-
.../CodeGen/AMDGPU/subreg-eliminate-dead.ll | 2 +-
llvm/test/CodeGen/AMDGPU/swizzle-export.ll | 14 +-
.../test/CodeGen/AMDGPU/tex-clause-antidep.ll | 2 +-
.../CodeGen/AMDGPU/texture-input-merge.ll | 6 +-
llvm/test/CodeGen/AMDGPU/trunc-combine.ll | 8 +-
.../AMDGPU/undefined-subreg-liverange.ll | 4 +-
.../CodeGen/AMDGPU/unigine-liveness-crash.ll | 4 +-
llvm/test/CodeGen/AMDGPU/unpack-half.ll | 2 +-
llvm/test/CodeGen/AMDGPU/v_pack.ll | 8 +-
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 8 +-
.../AMDGPU/vector-legalizer-divergence.ll | 2 +-
.../CodeGen/AMDGPU/vector_shuffle.packed.ll | 6 +-
...vgpr-spill-emergency-stack-slot-compute.ll | 2 +-
.../AMDGPU/vgpr-spill-emergency-stack-slot.ll | 2 +-
.../CodeGen/AMDGPU/widen-vselect-and-mask.ll | 16 +-
llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll | 4 +-
llvm/test/CodeGen/AMDGPU/xor3.ll | 4 +-
145 files changed, 660 insertions(+), 662 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
index 4ddbb0afd7fc5..357e9d6530ce8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
@@ -266,7 +266,7 @@ define <4 x float> @v_uitofp_unpack_i32_to_v4f32(i32 %arg0) nounwind {
%mask.lshr.24 = and i32 %lshr.24, 255
%cvt3 = uitofp i32 %mask.lshr.24 to float
- %ins.0 = insertelement <4 x float> undef, float %cvt0, i32 0
+ %ins.0 = insertelement <4 x float> poison, float %cvt0, i32 0
%ins.1 = insertelement <4 x float> %ins.0, float %cvt1, i32 1
%ins.2 = insertelement <4 x float> %ins.1, float %cvt2, i32 2
%ins.3 = insertelement <4 x float> %ins.2, float %cvt3, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
index 6bf0bd8d67fbe..80a9fc509d6ea 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
@@ -1061,7 +1061,6 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF1]](<3 x s32>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
@@ -1081,7 +1080,7 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
%load2 = load volatile i32, ptr addrspace(3) undef
%load3 = load volatile i32, ptr addrspace(3) undef
- %insert.0 = insertelement <3 x i32> undef, i32 %load0, i32 0
+ %insert.0 = insertelement <3 x i32> poison, i32 %load0, i32 0
%insert.1 = insertelement <3 x i32> %insert.0, i32 %load1, i32 1
%insert.2 = insertelement <3 x i32> %insert.1, i32 %load2, i32 2
%insert.3 = insertvalue { <3 x i32>, i32 } poison, <3 x i32> %insert.2, 0
@@ -1097,7 +1096,6 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF1]](<3 x s32>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
@@ -1117,7 +1115,7 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
%load2 = load volatile float, ptr addrspace(3) undef
%load3 = load volatile i32, ptr addrspace(3) undef
- %insert.0 = insertelement <3 x float> undef, float %load0, i32 0
+ %insert.0 = insertelement <3 x float> poison, float %load0, i32 0
%insert.1 = insertelement <3 x float> %insert.0, float %load1, i32 1
%insert.2 = insertelement <3 x float> %insert.1, float %load2, i32 2
%insert.3 = insertvalue { <3 x float>, i32 } poison, <3 x float> %insert.2, 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
index c35952c5b77ed..b68cc982731ed 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
@@ -17,7 +17,7 @@ bb:
%load = load <2 x i32>, ptr addrspace(3) %gep, align 4
%v1 = extractelement <2 x i32> %load, i32 0
%v2 = extractelement <2 x i32> %load, i32 1
- %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
+ %v3 = insertelement <2 x i32> poison, i32 %v2, i32 0
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
store <2 x i32> %v4, ptr addrspace(3) %gep, align 4
ret void
@@ -39,7 +39,7 @@ bb:
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
- %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
+ %v5 = insertelement <4 x i32> poison, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
@@ -62,7 +62,7 @@ bb:
%v1 = extractelement <3 x i32> %load, i32 0
%v2 = extractelement <3 x i32> %load, i32 1
%v3 = extractelement <3 x i32> %load, i32 2
- %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
+ %v5 = insertelement <3 x i32> poison, i32 %v3, i32 0
%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
store <3 x i32> %v7, ptr addrspace(3) %gep, align 4
@@ -79,7 +79,7 @@ bb:
%load = load <2 x i32>, ptr addrspace(3) %gep, align 8
%v1 = extractelement <2 x i32> %load, i32 0
%v2 = extractelement <2 x i32> %load, i32 1
- %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
+ %v3 = insertelement <2 x i32> poison, i32 %v2, i32 0
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
store <2 x i32> %v4, ptr addrspace(3) %gep, align 8
ret void
@@ -96,7 +96,7 @@ bb:
%v1 = extractelement <3 x i32> %load, i32 0
%v2 = extractelement <3 x i32> %load, i32 1
%v3 = extractelement <3 x i32> %load, i32 2
- %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
+ %v5 = insertelement <3 x i32> poison, i32 %v3, i32 0
%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
store <3 x i32> %v7, ptr addrspace(3) %gep, align 16
@@ -121,7 +121,7 @@ bb:
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
- %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
+ %v5 = insertelement <4 x i32> poison, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
index b26ddbdd7a342..bba0e08ee6341 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
@@ -33,13 +33,13 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_flat(i32 %node_ptr, float
; GCN-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[0:3]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
- %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
+ %ray_origin0 = insertelement <3 x float> poison, float %ray_origin_x, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
- %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
+ %ray_dir0 = insertelement <3 x float> poison, float %ray_dir_x, i32 0
%ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
%ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
- %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
+ %ray_inv_dir0 = insertelement <3 x float> poison, float %ray_inv_dir_x, i32 0
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
@@ -96,13 +96,13 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_flat(<2 x i32> %node_ptr
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
%node_ptr = bitcast <2 x i32> %node_ptr_vec to i64
- %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
+ %ray_origin0 = insertelement <3 x float> poison, float %ray_origin_x, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
- %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
+ %ray_dir0 = insertelement <3 x float> poison, float %ray_dir_x, i32 0
%ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
%ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
- %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
+ %ray_inv_dir0 = insertelement <3 x float> poison, float %ray_inv_dir_x, i32 0
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
@@ -725,13 +725,13 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
%node_ptr = load i32, ptr %gep_node_ptr, align 4
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
%ray_extent = load float, ptr %gep_ray, align 4
- %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
+ %ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
- %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
+ %ray_dir0 = insertelement <3 x float> poison, float 3.0, i32 0
%ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
%ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
- %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
+ %ray_inv_dir0 = insertelement <3 x float> poison, float 6.0, i32 0
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
@@ -829,13 +829,13 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
%node_ptr = load i32, ptr %gep_node_ptr, align 4
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
%ray_extent = load float, ptr %gep_ray, align 4
- %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
+ %ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
- %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
+ %ray_dir0 = insertelement <3 x half> poison, half 3.0, i32 0
%ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
%ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
- %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
+ %ray_inv_dir0 = insertelement <3 x half> poison, half 6.0, i32 0
%ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
%ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
@@ -911,13 +911,13 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
%ray_extent = load float, ptr %gep_ray, align 4
- %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
+ %ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
- %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
+ %ray_dir0 = insertelement <3 x float> poison, float 3.0, i32 0
%ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
%ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
- %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
+ %ray_inv_dir0 = insertelement <3 x float> poison, float 6.0, i32 0
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
@@ -985,13 +985,13 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
%ray_extent = load float, ptr %gep_ray, align 4
- %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
+ %ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
- %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
+ %ray_dir0 = insertelement <3 x half> poison, half 3.0, i32 0
%ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
%ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
- %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
+ %ray_inv_dir0 = insertelement <3 x half> poison, half 6.0, i32 0
%ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
%ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
index 0c9ff3eee8231..2a200259a93d2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
@@ -368,7 +368,7 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
%elt.1 = extractelement <2 x i32> %cast, i32 1
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
%res.1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.1)
- %ins.0 = insertelement <2 x i32> undef, i32 %res.0, i32 0
+ %ins.0 = insertelement <2 x i32> poison, i32 %res.0, i32 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 %res.0, i32 1
%cast.back = bitcast <2 x i32> %ins.1 to i64
ret i64 %cast.back
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
index df645888626c6..2bb42308d935c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
@@ -358,7 +358,7 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
%elt.1 = extractelement <2 x i32> %cast, i32 1
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
%res.1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.1)
- %ins.0 = insertelement <2 x i32> undef, i32 %res.0, i32 0
+ %ins.0 = insertelement <2 x i32> poison, i32 %res.0, i32 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 %res.0, i32 1
%cast.back = bitcast <2 x i32> %ins.1 to i64
ret i64 %cast.back
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
index f5a901b024ef5..a292266fbbf0d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
@@ -355,7 +355,7 @@ define amdgpu_ps i64 @s_udiv_i64(i64 inreg %num, i64 inreg %den) {
%elt.1 = extractelement <2 x i32> %cast, i32 1
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
%res.1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.1)
- %ins.0 = insertelement <2 x i32> undef, i32 %res.0, i32 0
+ %ins.0 = insertelement <2 x i32> poison, i32 %res.0, i32 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 %res.0, i32 1
%cast.back = bitcast <2 x i32> %ins.1 to i64
ret i64 %cast.back
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
index 2be4b52198b45..f29c2c2484456 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
@@ -349,7 +349,7 @@ define amdgpu_ps i64 @s_urem_i64(i64 inreg %num, i64 inreg %den) {
%elt.1 = extractelement <2 x i32> %cast, i32 1
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
%res.1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.1)
- %ins.0 = insertelement <2 x i32> undef, i32 %res.0, i32 0
+ %ins.0 = insertelement <2 x i32> poison, i32 %res.0, i32 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 %res.0, i32 1
%cast.back = bitcast <2 x i32> %ins.1 to i64
ret i64 %cast.back
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
index 43322b1e23412..17b6f5072116d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
@@ -90,7 +90,7 @@ entry:
%xor = xor i32 %a, %b
%r0.val = xor i32 %xor, -1
%r1.val = add i32 %xor, %a
- %ins0 = insertelement <2 x i32> undef, i32 %r0.val, i32 0
+ %ins0 = insertelement <2 x i32> poison, i32 %r0.val, i32 0
%ins1 = insertelement <2 x i32> %ins0, i32 %r1.val, i32 1
ret <2 x i32> %ins1
}
@@ -196,7 +196,7 @@ define amdgpu_ps <2 x i64> @scalar_xnor_i64_mul_use(i64 inreg %a, i64 inreg %b)
%xor = xor i64 %a, %b
%r0.val = xor i64 %xor, -1
%r1.val = add i64 %xor, %a
- %ins0 = insertelement <2 x i64> undef, i64 %r0.val, i32 0
+ %ins0 = insertelement <2 x i64> poison, i64 %r0.val, i32 0
%ins1 = insertelement <2 x i64> %ins0, i64 %r1.val, i32 1
ret <2 x i64> %ins1
}
diff --git a/llvm/test/CodeGen/AMDGPU/add3.ll b/llvm/test/CodeGen/AMDGPU/add3.ll
index d3f9c2d0fbc54..0d80296bb67b6 100644
--- a/llvm/test/CodeGen/AMDGPU/add3.ll
+++ b/llvm/test/CodeGen/AMDGPU/add3.ll
@@ -181,7 +181,7 @@ define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x
%inner = add i32 %a, %b
%outer = add i32 %inner, %c
%x1 = mul i32 %outer, %x
- %r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
+ %r1 = insertelement <2 x i32> poison, i32 %outer, i32 0
%r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
%bc = bitcast <2 x i32> %r0 to <2 x float>
ret <2 x float> %bc
@@ -207,7 +207,7 @@ define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
; GFX10-NEXT: ; return to shader part epilog
%inner = add i32 %a, %b
%outer = add i32 %inner, %c
- %r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
+ %r1 = insertelement <2 x i32> poison, i32 %inner, i32 0
%r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
%bc = bitcast <2 x i32> %r0 to <2 x float>
ret <2 x float> %bc
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll b/llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
index 2aea4497c12ba..b610fca02f92e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
@@ -17,7 +17,7 @@ define amdgpu_hs void @_amdgpu_hs_main(i32 inreg %arg, i32 inreg %arg1, i32 inre
.beginls: ; preds = %.entry
%tmp15 = extractelement <6 x i32> %arg8, i32 3
- %.0.vec.insert.i = insertelement <2 x i32> undef, i32 %tmp15, i32 0
+ %.0.vec.insert.i = insertelement <2 x i32> poison, i32 %tmp15, i32 0
%.4.vec.insert.i = shufflevector <2 x i32> %.0.vec.insert.i, <2 x i32> undef, <2 x i32> <i32 0, i32 3>
%tmp16 = bitcast <2 x i32> %.4.vec.insert.i to i64
br label %.endls
diff --git a/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll b/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
index 07e39d798f58d..8bcef24c8e23d 100644
--- a/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
@@ -36,7 +36,7 @@ bb:
%tmp21 = getelementptr inbounds <8 x i8>, ptr addrspace(1) %arg, i64 4
%tmp23 = load <16 x i8>, ptr addrspace(1) %tmp21, align 16
%tmp24 = extractelement <16 x i8> %tmp23, i64 3
- %tmp1 = insertelement <16 x i8> undef, i8 %tmp3, i32 2
+ %tmp1 = insertelement <16 x i8> poison, i8 %tmp3, i32 2
%tmp4 = insertelement <16 x i8> %tmp1, i8 0, i32 3
%tmp5 = insertelement <16 x i8> %tmp4, i8 0, i32 4
%tmp7 = insertelement <16 x i8> %tmp5, i8 %tmp6, i32 5
diff --git a/llvm/test/CodeGen/AMDGPU/anyext.ll b/llvm/test/CodeGen/AMDGPU/anyext.ll
index 6e16c90033273..f0aa141e65a5c 100644
--- a/llvm/test/CodeGen/AMDGPU/anyext.ll
+++ b/llvm/test/CodeGen/AMDGPU/anyext.ll
@@ -187,7 +187,7 @@ define amdgpu_kernel void @anyext_v2i16_to_v2i32() #0 {
; GFX9-NEXT: s_endpgm
bb:
%tmp = load i16, ptr addrspace(1) undef, align 2
- %tmp2 = insertelement <2 x i16> undef, i16 %tmp, i32 1
+ %tmp2 = insertelement <2 x i16> poison, i16 %tmp, i32 1
%tmp4 = and <2 x i16> %tmp2, <i16 -32767, i16 -32767>
%tmp5 = zext <2 x i16> %tmp4 to <2 x i32>
%tmp6 = shl nuw <2 x i32> %tmp5, <i32 16, i32 16>
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
index 0b5d47df2cc35..4c01e583713a7 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
@@ -189,7 +189,7 @@ define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16(float %a, float %b) {
entry:
%a.cvt = fptrunc float %a to bfloat
%b.cvt = fptrunc float %b to bfloat
- %v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
+ %v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
%ret = bitcast <2 x bfloat> %v2.2 to float
ret float %ret
@@ -226,7 +226,7 @@ entry:
%a.cvt = fptrunc float %a.neg to bfloat
%b.abs = call float @llvm.fabs.f32(float %b)
%b.cvt = fptrunc float %b.abs to bfloat
- %v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
+ %v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
%ret = bitcast <2 x bfloat> %v2.2 to float
ret float %ret
diff --git a/llvm/test/CodeGen/AMDGPU/bfi_nested.ll b/llvm/test/CodeGen/AMDGPU/bfi_nested.ll
index 4b38215ebc597..3d52c158a6017 100644
--- a/llvm/test/CodeGen/AMDGPU/bfi_nested.ll
+++ b/llvm/test/CodeGen/AMDGPU/bfi_nested.ll
@@ -297,7 +297,7 @@ define amdgpu_kernel void @v_bfi_dont_applied_for_scalar_ops(ptr addrspace(1) %o
; GCN-NEXT: s_endpgm
%shift = lshr i32 %b, 16
%tr = trunc i32 %shift to i16
- %tmp = insertelement <2 x i16> undef, i16 %a, i32 0
+ %tmp = insertelement <2 x i16> poison, i16 %a, i32 0
%vec = insertelement <2 x i16> %tmp, i16 %tr, i32 1
%val = bitcast <2 x i16> %vec to i32
store i32 %val, ptr addrspace(1) %out, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/big_alu.ll b/llvm/test/CodeGen/AMDGPU/big_alu.ll
index 0daa14a63f21a..b3b6259838341 100644
--- a/llvm/test/CodeGen/AMDGPU/big_alu.ll
+++ b/llvm/test/CodeGen/AMDGPU/big_alu.ll
@@ -90,11 +90,11 @@ main_body:
br i1 %tmp81, label %IF137, label %ENDIF136
IF137: ; preds = %main_body
- %tmp82 = insertelement <4 x float> undef, float %tmp30, i32 0
+ %tmp82 = insertelement <4 x float> poison, float %tmp30, i32 0
%tmp83 = insertelement <4 x float> %tmp82, float %tmp31, i32 1
%tmp84 = insertelement <4 x float> %tmp83, float %tmp32, i32 2
%tmp85 = insertelement <4 x float> %tmp84, float 0.000000e+00, i32 3
- %tmp86 = insertelement <4 x float> undef, float %tmp30, i32 0
+ %tmp86 = insertelement <4 x float> poison, float %tmp30, i32 0
%tmp87 = insertelement <4 x float> %tmp86, float %tmp31, i32 1
%tmp88 = insertelement <4 x float> %tmp87, float %tmp32, i32 2
%tmp89 = insertelement <4 x float> %tmp88, float 0.000000e+00, i32 3
@@ -103,20 +103,20 @@ IF137: ; preds = %main_body
%tmp92 = fmul float %tmp30, %tmp91
%tmp93 = fmul float %tmp31, %tmp91
%tmp94 = fmul float %tmp32, %tmp91
- %tmp95 = insertelement <4 x float> undef, float %tmp92, i32 0
+ %tmp95 = insertelement <4 x float> poison, float %tmp92, i32 0
%tmp96 = insertelement <4 x float> %tmp95, float %tmp93, i32 1
%tmp97 = insertelement <4 x float> %tmp96, float %tmp94, i32 2
%tmp98 = insertelement <4 x float> %tmp97, float 0.000000e+00, i32 3
- %tmp99 = insertelement <4 x float> undef, float %tmp37, i32 0
+ %tmp99 = insertelement <4 x float> poison, float %tmp37, i32 0
%tmp100 = insertelement <4 x float> %tmp99, float %tmp38, i32 1
%tmp101 = insertelement <4 x float> %tmp100, float %tmp39, i32 2
%tmp102 = insertelement <4 x float> %tmp101, float 0.000000e+00, i32 3
%tmp103 = call float @llvm.r600.dot4(<4 x float> %tmp98, <4 x float> %tmp102)
- %tmp104 = insertelement <4 x float> undef, float %tmp92, i32 0
+ %tmp104 = insertelement <4 x float> poison, float %tmp92, i32 0
%tmp105 = insertelement <4 x float> %tmp104, float %tmp93, i32 1
%tmp106 = insertelement <4 x float> %tmp105, float %tmp94, i32 2
%tmp107 = insertelement <4 x float> %tmp106, float 0.000000e+00, i32 3
- %tmp108 = insertelement <4 x float> undef, float %tmp40, i32 0
+ %tmp108 = insertelement <4 x float> poison, float %tmp40, i32 0
%tmp109 = insertelement <4 x float> %tmp108, float %tmp41, i32 1
%tmp110 = insertelement <4 x float> %tmp109, float %tmp42, i32 2
%tmp111 = insertelement <4 x float> %tmp110, float 0.000000e+00, i32 3
@@ -124,11 +124,11 @@ IF137: ; preds = %main_body
%tmp113 = fsub float -0.000000e+00, %tmp92
%tmp114 = fsub float -0.000000e+00, %tmp93
%tmp115 = fsub float -0.000000e+00, %tmp94
- %tmp116 = insertelement <4 x float> undef, float %tmp34, i32 0
+ %tmp116 = insertelement <4 x float> poison, float %tmp34, i32 0
%tmp117 = insertelement <4 x float> %tmp116, float %tmp35, i32 1
%tmp118 = insertelement <4 x float> %tmp117, float %tmp36, i32 2
%tmp119 = insertelement <4 x float> %tmp118, float 0.000000e+00, i32 3
- %tmp120 = insertelement <4 x float> undef, float %tmp113, i32 0
+ %tmp120 = insertelement <4 x float> poison, float %tmp113, i32 0
%tmp121 = insertelement <4 x float> %tmp120, float %tmp114, i32 1
%tmp122 = insertelement <4 x float> %tmp121, float %tmp115, i32 2
%tmp123 = insertelement <4 x float> %tmp122, float 0.000000e+00, i32 3
@@ -155,7 +155,7 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp138 = fmul float %tmp26, 0x3F847AE140000000
%tmp139 = fmul float %tmp27, 0x3F847AE140000000
%tmp140 = fmul float %tmp28, 0x3F847AE140000000
- %tmp141 = insertelement <4 x float> undef, float %tmp138, i32 0
+ %tmp141 = insertelement <4 x float> poison, float %tmp138, i32 0
%tmp142 = insertelement <4 x float> %tmp141, float %tmp139, i32 1
%tmp143 = insertelement <4 x float> %tmp142, float %tmp140, i32 2
%tmp144 = insertelement <4 x float> %tmp143, float 0.000000e+00, i32 3
@@ -163,7 +163,7 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp146 = extractelement <4 x float> %tmp144, i32 1
%tmp147 = extractelement <4 x float> %tmp144, i32 2
%tmp148 = extractelement <4 x float> %tmp144, i32 3
- %tmp149 = insertelement <4 x float> undef, float %tmp145, i32 0
+ %tmp149 = insertelement <4 x float> poison, float %tmp145, i32 0
%tmp150 = insertelement <4 x float> %tmp149, float %tmp146, i32 1
%tmp151 = insertelement <4 x float> %tmp150, float %tmp147, i32 2
%tmp152 = insertelement <4 x float> %tmp151, float %tmp148, i32 3
@@ -176,7 +176,7 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp159 = fmul float %tmp26, 0x3F45A07B40000000
%tmp160 = fmul float %tmp27, 0x3F45A07B40000000
%tmp161 = fmul float %tmp28, 0x3F45A07B40000000
- %tmp162 = insertelement <4 x float> undef, float %tmp159, i32 0
+ %tmp162 = insertelement <4 x float> poison, float %tmp159, i32 0
%tmp163 = insertelement <4 x float> %tmp162, float %tmp160, i32 1
%tmp164 = insertelement <4 x float> %tmp163, float %tmp161, i32 2
%tmp165 = insertelement <4 x float> %tmp164, float 0.000000e+00, i32 3
@@ -184,7 +184,7 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp167 = extractelement <4 x float> %tmp165, i32 1
%tmp168 = extractelement <4 x float> %tmp165, i32 2
%tmp169 = extractelement <4 x float> %tmp165, i32 3
- %tmp170 = insertelement <4 x float> undef, float %tmp166, i32 0
+ %tmp170 = insertelement <4 x float> poison, float %tmp166, i32 0
%tmp171 = insertelement <4 x float> %tmp170, float %tmp167, i32 1
%tmp172 = insertelement <4 x float> %tmp171, float %tmp168, i32 2
%tmp173 = insertelement <4 x float> %tmp172, float %tmp169, i32 3
@@ -251,28 +251,28 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp227 = fmul float %clamp.i14, %tmp226
%tmp228 = fmul float %tmp26, 0x3F368B5CC0000000
%tmp229 = fmul float %tmp27, 0x3F368B5CC0000000
- %tmp230 = insertelement <4 x float> undef, float %tmp228, i32 0
+ %tmp230 = insertelement <4 x float> poison, float %tmp228, i32 0
%tmp231 = insertelement <4 x float> %tmp230, float %tmp229, i32 1
%tmp232 = insertelement <4 x float> %tmp231, float 0.000000e+00, i32 2
%tmp233 = insertelement <4 x float> %tmp232, float 0.000000e+00, i32 3
%tmp234 = extractelement <4 x float> %tmp233, i32 0
%tmp235 = extractelement <4 x float> %tmp233, i32 1
- %tmp236 = insertelement <4 x float> undef, float %tmp234, i32 0
+ %tmp236 = insertelement <4 x float> poison, float %tmp234, i32 0
%tmp237 = insertelement <4 x float> %tmp236, float %tmp235, i32 1
- %tmp238 = insertelement <4 x float> %tmp237, float undef, i32 2
- %tmp239 = insertelement <4 x float> %tmp238, float undef, i32 3
+ %tmp238 = insertelement <4 x float> %tmp237, float poison, i32 2
+ %tmp239 = insertelement <4 x float> %tmp238, float poison, i32 3
%tmp240 = shufflevector <4 x float> %tmp239, <4 x float> %tmp239, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp241 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp240, i32 0, i32 0, i32 0, i32 17, i32 1, i32 1, i32 1, i32 1, i32 1)
%tmp242 = extractelement <4 x float> %tmp241, i32 0
- %tmp243 = insertelement <4 x float> undef, float %tmp242, i32 0
+ %tmp243 = insertelement <4 x float> poison, float %tmp242, i32 0
%tmp244 = insertelement <4 x float> %tmp243, float %tmp229, i32 1
%tmp245 = insertelement <4 x float> %tmp244, float 0.000000e+00, i32 2
%tmp246 = insertelement <4 x float> %tmp245, float 0.000000e+00, i32 3
%tmp247 = extractelement <4 x float> %tmp246, i32 0
- %tmp248 = insertelement <4 x float> undef, float %tmp247, i32 0
- %tmp249 = insertelement <4 x float> %tmp248, float undef, i32 1
- %tmp250 = insertelement <4 x float> %tmp249, float undef, i32 2
- %tmp251 = insertelement <4 x float> %tmp250, float undef, i32 3
+ %tmp248 = insertelement <4 x float> poison, float %tmp247, i32 0
+ %tmp249 = insertelement <4 x float> %tmp248, float poison, i32 1
+ %tmp250 = insertelement <4 x float> %tmp249, float poison, i32 2
+ %tmp251 = insertelement <4 x float> %tmp250, float poison, i32 3
%tmp252 = shufflevector <4 x float> %tmp251, <4 x float> %tmp251, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp253 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp252, i32 0, i32 0, i32 0, i32 18, i32 2, i32 1, i32 1, i32 1, i32 1)
%tmp254 = extractelement <4 x float> %tmp253, i32 0
@@ -312,16 +312,16 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp285 = fmul float %clamp.i8, %tmp284
%tmp286 = fmul float %tmp26, 0x3F22DFD6A0000000
%tmp287 = fmul float %tmp27, 0x3F22DFD6A0000000
- %tmp288 = insertelement <4 x float> undef, float %tmp286, i32 0
+ %tmp288 = insertelement <4 x float> poison, float %tmp286, i32 0
%tmp289 = insertelement <4 x float> %tmp288, float %tmp287, i32 1
%tmp290 = insertelement <4 x float> %tmp289, float 0.000000e+00, i32 2
%tmp291 = insertelement <4 x float> %tmp290, float 0.000000e+00, i32 3
%tmp292 = extractelement <4 x float> %tmp291, i32 0
%tmp293 = extractelement <4 x float> %tmp291, i32 1
- %tmp294 = insertelement <4 x float> undef, float %tmp292, i32 0
+ %tmp294 = insertelement <4 x float> poison, float %tmp292, i32 0
%tmp295 = insertelement <4 x float> %tmp294, float %tmp293, i32 1
- %tmp296 = insertelement <4 x float> %tmp295, float undef, i32 2
- %tmp297 = insertelement <4 x float> %tmp296, float undef, i32 3
+ %tmp296 = insertelement <4 x float> %tmp295, float poison, i32 2
+ %tmp297 = insertelement <4 x float> %tmp296, float poison, i32 3
%tmp298 = shufflevector <4 x float> %tmp297, <4 x float> %tmp297, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp299 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp298, i32 0, i32 0, i32 0, i32 19, i32 3, i32 1, i32 1, i32 1, i32 1)
%tmp300 = extractelement <4 x float> %tmp299, i32 0
@@ -347,11 +347,11 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp320 = fadd float %tmp319, %tmp314
%tmp321 = fmul float %temp70.0, %tmp36
%tmp322 = fadd float %tmp321, %tmp316
- %tmp323 = insertelement <4 x float> undef, float %tmp318, i32 0
+ %tmp323 = insertelement <4 x float> poison, float %tmp318, i32 0
%tmp324 = insertelement <4 x float> %tmp323, float %tmp320, i32 1
%tmp325 = insertelement <4 x float> %tmp324, float %tmp322, i32 2
%tmp326 = insertelement <4 x float> %tmp325, float 0.000000e+00, i32 3
- %tmp327 = insertelement <4 x float> undef, float %tmp318, i32 0
+ %tmp327 = insertelement <4 x float> poison, float %tmp318, i32 0
%tmp328 = insertelement <4 x float> %tmp327, float %tmp320, i32 1
%tmp329 = insertelement <4 x float> %tmp328, float %tmp322, i32 2
%tmp330 = insertelement <4 x float> %tmp329, float 0.000000e+00, i32 3
@@ -380,11 +380,11 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp353 = fsub float -0.000000e+00, %result.i
%tmp354 = fsub float -0.000000e+00, %tmp347
%tmp355 = fadd float %tmp353, %tmp354
- %tmp356 = insertelement <4 x float> undef, float %tmp43, i32 0
+ %tmp356 = insertelement <4 x float> poison, float %tmp43, i32 0
%tmp357 = insertelement <4 x float> %tmp356, float %tmp44, i32 1
%tmp358 = insertelement <4 x float> %tmp357, float %tmp45, i32 2
%tmp359 = insertelement <4 x float> %tmp358, float 0.000000e+00, i32 3
- %tmp360 = insertelement <4 x float> undef, float %tmp43, i32 0
+ %tmp360 = insertelement <4 x float> poison, float %tmp43, i32 0
%tmp361 = insertelement <4 x float> %tmp360, float %tmp44, i32 1
%tmp362 = insertelement <4 x float> %tmp361, float %tmp45, i32 2
%tmp363 = insertelement <4 x float> %tmp362, float 0.000000e+00, i32 3
@@ -407,11 +407,11 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp379 = fsub float -0.000000e+00, %result.i
%tmp380 = fsub float -0.000000e+00, %tmp347
%tmp381 = fadd float %tmp379, %tmp380
- %tmp382 = insertelement <4 x float> undef, float %tmp43, i32 0
+ %tmp382 = insertelement <4 x float> poison, float %tmp43, i32 0
%tmp383 = insertelement <4 x float> %tmp382, float %tmp44, i32 1
%tmp384 = insertelement <4 x float> %tmp383, float %tmp45, i32 2
%tmp385 = insertelement <4 x float> %tmp384, float 0.000000e+00, i32 3
- %tmp386 = insertelement <4 x float> undef, float %tmp43, i32 0
+ %tmp386 = insertelement <4 x float> poison, float %tmp43, i32 0
%tmp387 = insertelement <4 x float> %tmp386, float %tmp44, i32 1
%tmp388 = insertelement <4 x float> %tmp387, float %tmp45, i32 2
%tmp389 = insertelement <4 x float> %tmp388, float 0.000000e+00, i32 3
@@ -492,16 +492,16 @@ IF140: ; preds = %LOOP
%tmp422 = fadd float %tmp421, %tmp22
%tmp423 = fmul float %tmp130, %temp92.0
%tmp424 = fadd float %tmp423, %tmp23
- %tmp425 = insertelement <4 x float> undef, float %tmp422, i32 0
+ %tmp425 = insertelement <4 x float> poison, float %tmp422, i32 0
%tmp426 = insertelement <4 x float> %tmp425, float %tmp424, i32 1
%tmp427 = insertelement <4 x float> %tmp426, float 0.000000e+00, i32 2
%tmp428 = insertelement <4 x float> %tmp427, float 0.000000e+00, i32 3
%tmp429 = extractelement <4 x float> %tmp428, i32 0
%tmp430 = extractelement <4 x float> %tmp428, i32 1
- %tmp431 = insertelement <4 x float> undef, float %tmp429, i32 0
+ %tmp431 = insertelement <4 x float> poison, float %tmp429, i32 0
%tmp432 = insertelement <4 x float> %tmp431, float %tmp430, i32 1
- %tmp433 = insertelement <4 x float> %tmp432, float undef, i32 2
- %tmp434 = insertelement <4 x float> %tmp433, float undef, i32 3
+ %tmp433 = insertelement <4 x float> %tmp432, float poison, i32 2
+ %tmp434 = insertelement <4 x float> %tmp433, float poison, i32 3
%tmp435 = shufflevector <4 x float> %tmp434, <4 x float> %tmp434, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp436 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp435, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1)
%tmp437 = extractelement <4 x float> %tmp436, i32 3
@@ -518,16 +518,16 @@ ENDIF139: ; preds = %LOOP
%tmp445 = fadd float %tmp444, %tmp22
%tmp446 = fmul float %tmp130, %tmp443
%tmp447 = fadd float %tmp446, %tmp23
- %tmp448 = insertelement <4 x float> undef, float %tmp445, i32 0
+ %tmp448 = insertelement <4 x float> poison, float %tmp445, i32 0
%tmp449 = insertelement <4 x float> %tmp448, float %tmp447, i32 1
%tmp450 = insertelement <4 x float> %tmp449, float 0.000000e+00, i32 2
%tmp451 = insertelement <4 x float> %tmp450, float 0.000000e+00, i32 3
%tmp452 = extractelement <4 x float> %tmp451, i32 0
%tmp453 = extractelement <4 x float> %tmp451, i32 1
- %tmp454 = insertelement <4 x float> undef, float %tmp452, i32 0
+ %tmp454 = insertelement <4 x float> poison, float %tmp452, i32 0
%tmp455 = insertelement <4 x float> %tmp454, float %tmp453, i32 1
- %tmp456 = insertelement <4 x float> %tmp455, float undef, i32 2
- %tmp457 = insertelement <4 x float> %tmp456, float undef, i32 3
+ %tmp456 = insertelement <4 x float> %tmp455, float poison, i32 2
+ %tmp457 = insertelement <4 x float> %tmp456, float poison, i32 3
%tmp458 = shufflevector <4 x float> %tmp457, <4 x float> %tmp457, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp459 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp458, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1)
%tmp460 = extractelement <4 x float> %tmp459, i32 3
@@ -563,16 +563,16 @@ ENDIF145: ; preds = %IF146, %IF140
%tmp482 = fadd float %tmp481, %tmp22
%tmp483 = fmul float %tmp130, %tmp479
%tmp484 = fadd float %tmp483, %tmp23
- %tmp485 = insertelement <4 x float> undef, float %tmp482, i32 0
+ %tmp485 = insertelement <4 x float> poison, float %tmp482, i32 0
%tmp486 = insertelement <4 x float> %tmp485, float %tmp484, i32 1
%tmp487 = insertelement <4 x float> %tmp486, float 0.000000e+00, i32 2
%tmp488 = insertelement <4 x float> %tmp487, float %tmp437, i32 3
%tmp489 = extractelement <4 x float> %tmp488, i32 0
%tmp490 = extractelement <4 x float> %tmp488, i32 1
- %tmp491 = insertelement <4 x float> undef, float %tmp489, i32 0
+ %tmp491 = insertelement <4 x float> poison, float %tmp489, i32 0
%tmp492 = insertelement <4 x float> %tmp491, float %tmp490, i32 1
- %tmp493 = insertelement <4 x float> %tmp492, float undef, i32 2
- %tmp494 = insertelement <4 x float> %tmp493, float undef, i32 3
+ %tmp493 = insertelement <4 x float> %tmp492, float poison, i32 2
+ %tmp494 = insertelement <4 x float> %tmp493, float poison, i32 3
%tmp495 = shufflevector <4 x float> %tmp494, <4 x float> %tmp494, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp496 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp495, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1)
%tmp497 = extractelement <4 x float> %tmp496, i32 3
@@ -598,16 +598,16 @@ ENDIF148: ; preds = %IF149, %ENDIF145
%tmp509 = fadd float %tmp508, %tmp22
%tmp510 = fmul float %tmp130, %tmp506
%tmp511 = fadd float %tmp510, %tmp23
- %tmp512 = insertelement <4 x float> undef, float %tmp509, i32 0
+ %tmp512 = insertelement <4 x float> poison, float %tmp509, i32 0
%tmp513 = insertelement <4 x float> %tmp512, float %tmp511, i32 1
%tmp514 = insertelement <4 x float> %tmp513, float 0.000000e+00, i32 2
%tmp515 = insertelement <4 x float> %tmp514, float %tmp497, i32 3
%tmp516 = extractelement <4 x float> %tmp515, i32 0
%tmp517 = extractelement <4 x float> %tmp515, i32 1
- %tmp518 = insertelement <4 x float> undef, float %tmp516, i32 0
+ %tmp518 = insertelement <4 x float> poison, float %tmp516, i32 0
%tmp519 = insertelement <4 x float> %tmp518, float %tmp517, i32 1
- %tmp520 = insertelement <4 x float> %tmp519, float undef, i32 2
- %tmp521 = insertelement <4 x float> %tmp520, float undef, i32 3
+ %tmp520 = insertelement <4 x float> %tmp519, float poison, i32 2
+ %tmp521 = insertelement <4 x float> %tmp520, float poison, i32 3
%tmp522 = shufflevector <4 x float> %tmp521, <4 x float> %tmp521, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp523 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp522, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1)
%tmp524 = extractelement <4 x float> %tmp523, i32 3
@@ -633,16 +633,16 @@ ENDIF151: ; preds = %IF152, %ENDIF148
%tmp536 = fadd float %tmp535, %tmp22
%tmp537 = fmul float %tmp130, %tmp533
%tmp538 = fadd float %tmp537, %tmp23
- %tmp539 = insertelement <4 x float> undef, float %tmp536, i32 0
+ %tmp539 = insertelement <4 x float> poison, float %tmp536, i32 0
%tmp540 = insertelement <4 x float> %tmp539, float %tmp538, i32 1
%tmp541 = insertelement <4 x float> %tmp540, float 0.000000e+00, i32 2
%tmp542 = insertelement <4 x float> %tmp541, float %tmp524, i32 3
%tmp543 = extractelement <4 x float> %tmp542, i32 0
%tmp544 = extractelement <4 x float> %tmp542, i32 1
- %tmp545 = insertelement <4 x float> undef, float %tmp543, i32 0
+ %tmp545 = insertelement <4 x float> poison, float %tmp543, i32 0
%tmp546 = insertelement <4 x float> %tmp545, float %tmp544, i32 1
- %tmp547 = insertelement <4 x float> %tmp546, float undef, i32 2
- %tmp548 = insertelement <4 x float> %tmp547, float undef, i32 3
+ %tmp547 = insertelement <4 x float> %tmp546, float poison, i32 2
+ %tmp548 = insertelement <4 x float> %tmp547, float poison, i32 3
%tmp549 = shufflevector <4 x float> %tmp548, <4 x float> %tmp548, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp550 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp549, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1)
%tmp551 = extractelement <4 x float> %tmp550, i32 3
@@ -667,16 +667,16 @@ ENDIF154: ; preds = %IF155, %ENDIF151
%tmp562 = fadd float %tmp561, %tmp22
%tmp563 = fmul float %tmp130, %tmp560
%tmp564 = fadd float %tmp563, %tmp23
- %tmp565 = insertelement <4 x float> undef, float %tmp562, i32 0
+ %tmp565 = insertelement <4 x float> poison, float %tmp562, i32 0
%tmp566 = insertelement <4 x float> %tmp565, float %tmp564, i32 1
%tmp567 = insertelement <4 x float> %tmp566, float 0.000000e+00, i32 2
%tmp568 = insertelement <4 x float> %tmp567, float %tmp551, i32 3
%tmp569 = extractelement <4 x float> %tmp568, i32 0
%tmp570 = extractelement <4 x float> %tmp568, i32 1
- %tmp571 = insertelement <4 x float> undef, float %tmp569, i32 0
+ %tmp571 = insertelement <4 x float> poison, float %tmp569, i32 0
%tmp572 = insertelement <4 x float> %tmp571, float %tmp570, i32 1
- %tmp573 = insertelement <4 x float> %tmp572, float undef, i32 2
- %tmp574 = insertelement <4 x float> %tmp573, float undef, i32 3
+ %tmp573 = insertelement <4 x float> %tmp572, float poison, i32 2
+ %tmp574 = insertelement <4 x float> %tmp573, float poison, i32 3
%tmp575 = shufflevector <4 x float> %tmp574, <4 x float> %tmp574, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp576 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp575, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1)
%tmp577 = extractelement <4 x float> %tmp576, i32 3
@@ -690,16 +690,16 @@ ENDIF154: ; preds = %IF155, %ENDIF151
%tmp584 = fadd float %tmp583, %tmp22
%tmp585 = fmul float %tmp130, %.temp92.4
%tmp586 = fadd float %tmp585, %tmp23
- %tmp587 = insertelement <4 x float> undef, float %tmp584, i32 0
+ %tmp587 = insertelement <4 x float> poison, float %tmp584, i32 0
%tmp588 = insertelement <4 x float> %tmp587, float %tmp586, i32 1
%tmp589 = insertelement <4 x float> %tmp588, float 0.000000e+00, i32 2
%tmp590 = insertelement <4 x float> %tmp589, float %tmp577, i32 3
%tmp591 = extractelement <4 x float> %tmp590, i32 0
%tmp592 = extractelement <4 x float> %tmp590, i32 1
- %tmp593 = insertelement <4 x float> undef, float %tmp591, i32 0
+ %tmp593 = insertelement <4 x float> poison, float %tmp591, i32 0
%tmp594 = insertelement <4 x float> %tmp593, float %tmp592, i32 1
- %tmp595 = insertelement <4 x float> %tmp594, float undef, i32 2
- %tmp596 = insertelement <4 x float> %tmp595, float undef, i32 3
+ %tmp595 = insertelement <4 x float> %tmp594, float poison, i32 2
+ %tmp596 = insertelement <4 x float> %tmp595, float poison, i32 3
%tmp597 = shufflevector <4 x float> %tmp596, <4 x float> %tmp596, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp598 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp597, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1)
%tmp599 = extractelement <4 x float> %tmp598, i32 0
@@ -735,11 +735,11 @@ IF161: ; preds = %ENDIF136
%one.sub.ac.i126 = fmul float %one.sub.a.i125, %tmp307
%mul.i127 = fmul float %result.i160, %tmp307
%result.i128 = fadd float %mul.i127, %one.sub.ac.i126
- %tmp613 = insertelement <4 x float> undef, float %tmp333, i32 0
+ %tmp613 = insertelement <4 x float> poison, float %tmp333, i32 0
%tmp614 = insertelement <4 x float> %tmp613, float %tmp334, i32 1
%tmp615 = insertelement <4 x float> %tmp614, float %tmp335, i32 2
%tmp616 = insertelement <4 x float> %tmp615, float 0.000000e+00, i32 3
- %tmp617 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp617 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp618 = insertelement <4 x float> %tmp617, float %tmp65, i32 1
%tmp619 = insertelement <4 x float> %tmp618, float %tmp67, i32 2
%tmp620 = insertelement <4 x float> %tmp619, float 0.000000e+00, i32 3
@@ -749,11 +749,11 @@ IF161: ; preds = %ENDIF136
%tmp624 = fmul float %tmp8, %tmp623
%tmp625 = fmul float %tmp13, %tmp623
%tmp626 = fmul float %tmp18, %tmp623
- %tmp627 = insertelement <4 x float> undef, float %tmp34, i32 0
+ %tmp627 = insertelement <4 x float> poison, float %tmp34, i32 0
%tmp628 = insertelement <4 x float> %tmp627, float %tmp35, i32 1
%tmp629 = insertelement <4 x float> %tmp628, float %tmp36, i32 2
%tmp630 = insertelement <4 x float> %tmp629, float 0.000000e+00, i32 3
- %tmp631 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp631 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp632 = insertelement <4 x float> %tmp631, float %tmp65, i32 1
%tmp633 = insertelement <4 x float> %tmp632, float %tmp67, i32 2
%tmp634 = insertelement <4 x float> %tmp633, float 0.000000e+00, i32 3
@@ -809,11 +809,11 @@ IF164: ; preds = %ENDIF160
%one.sub.ac.i110 = fmul float %one.sub.a.i109, %tmp307
%mul.i111 = fmul float %result.i160, %tmp307
%result.i112 = fadd float %mul.i111, %one.sub.ac.i110
- %tmp658 = insertelement <4 x float> undef, float %tmp333, i32 0
+ %tmp658 = insertelement <4 x float> poison, float %tmp333, i32 0
%tmp659 = insertelement <4 x float> %tmp658, float %tmp334, i32 1
%tmp660 = insertelement <4 x float> %tmp659, float %tmp335, i32 2
%tmp661 = insertelement <4 x float> %tmp660, float 0.000000e+00, i32 3
- %tmp662 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp662 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp663 = insertelement <4 x float> %tmp662, float %tmp65, i32 1
%tmp664 = insertelement <4 x float> %tmp663, float %tmp67, i32 2
%tmp665 = insertelement <4 x float> %tmp664, float 0.000000e+00, i32 3
@@ -823,11 +823,11 @@ IF164: ; preds = %ENDIF160
%tmp669 = fmul float %tmp8, %tmp668
%tmp670 = fmul float %tmp13, %tmp668
%tmp671 = fmul float %tmp18, %tmp668
- %tmp672 = insertelement <4 x float> undef, float %tmp34, i32 0
+ %tmp672 = insertelement <4 x float> poison, float %tmp34, i32 0
%tmp673 = insertelement <4 x float> %tmp672, float %tmp35, i32 1
%tmp674 = insertelement <4 x float> %tmp673, float %tmp36, i32 2
%tmp675 = insertelement <4 x float> %tmp674, float 0.000000e+00, i32 3
- %tmp676 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp676 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp677 = insertelement <4 x float> %tmp676, float %tmp65, i32 1
%tmp678 = insertelement <4 x float> %tmp677, float %tmp67, i32 2
%tmp679 = insertelement <4 x float> %tmp678, float 0.000000e+00, i32 3
@@ -883,11 +883,11 @@ IF167: ; preds = %ENDIF163
%one.sub.ac.i94 = fmul float %one.sub.a.i93, %tmp307
%mul.i95 = fmul float %result.i144, %tmp307
%result.i96 = fadd float %mul.i95, %one.sub.ac.i94
- %tmp703 = insertelement <4 x float> undef, float %tmp333, i32 0
+ %tmp703 = insertelement <4 x float> poison, float %tmp333, i32 0
%tmp704 = insertelement <4 x float> %tmp703, float %tmp334, i32 1
%tmp705 = insertelement <4 x float> %tmp704, float %tmp335, i32 2
%tmp706 = insertelement <4 x float> %tmp705, float 0.000000e+00, i32 3
- %tmp707 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp707 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp708 = insertelement <4 x float> %tmp707, float %tmp65, i32 1
%tmp709 = insertelement <4 x float> %tmp708, float %tmp67, i32 2
%tmp710 = insertelement <4 x float> %tmp709, float 0.000000e+00, i32 3
@@ -897,11 +897,11 @@ IF167: ; preds = %ENDIF163
%tmp714 = fmul float %tmp8, %tmp713
%tmp715 = fmul float %tmp13, %tmp713
%tmp716 = fmul float %tmp18, %tmp713
- %tmp717 = insertelement <4 x float> undef, float %tmp34, i32 0
+ %tmp717 = insertelement <4 x float> poison, float %tmp34, i32 0
%tmp718 = insertelement <4 x float> %tmp717, float %tmp35, i32 1
%tmp719 = insertelement <4 x float> %tmp718, float %tmp36, i32 2
%tmp720 = insertelement <4 x float> %tmp719, float 0.000000e+00, i32 3
- %tmp721 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp721 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp722 = insertelement <4 x float> %tmp721, float %tmp65, i32 1
%tmp723 = insertelement <4 x float> %tmp722, float %tmp67, i32 2
%tmp724 = insertelement <4 x float> %tmp723, float 0.000000e+00, i32 3
@@ -957,11 +957,11 @@ IF170: ; preds = %ENDIF166
%one.sub.ac.i78 = fmul float %one.sub.a.i77, %tmp307
%mul.i79 = fmul float %result.i144, %tmp307
%result.i80 = fadd float %mul.i79, %one.sub.ac.i78
- %tmp748 = insertelement <4 x float> undef, float %tmp333, i32 0
+ %tmp748 = insertelement <4 x float> poison, float %tmp333, i32 0
%tmp749 = insertelement <4 x float> %tmp748, float %tmp334, i32 1
%tmp750 = insertelement <4 x float> %tmp749, float %tmp335, i32 2
%tmp751 = insertelement <4 x float> %tmp750, float 0.000000e+00, i32 3
- %tmp752 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp752 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp753 = insertelement <4 x float> %tmp752, float %tmp65, i32 1
%tmp754 = insertelement <4 x float> %tmp753, float %tmp67, i32 2
%tmp755 = insertelement <4 x float> %tmp754, float 0.000000e+00, i32 3
@@ -971,11 +971,11 @@ IF170: ; preds = %ENDIF166
%tmp759 = fmul float %tmp8, %tmp758
%tmp760 = fmul float %tmp13, %tmp758
%tmp761 = fmul float %tmp18, %tmp758
- %tmp762 = insertelement <4 x float> undef, float %tmp34, i32 0
+ %tmp762 = insertelement <4 x float> poison, float %tmp34, i32 0
%tmp763 = insertelement <4 x float> %tmp762, float %tmp35, i32 1
%tmp764 = insertelement <4 x float> %tmp763, float %tmp36, i32 2
%tmp765 = insertelement <4 x float> %tmp764, float 0.000000e+00, i32 3
- %tmp766 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp766 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp767 = insertelement <4 x float> %tmp766, float %tmp65, i32 1
%tmp768 = insertelement <4 x float> %tmp767, float %tmp67, i32 2
%tmp769 = insertelement <4 x float> %tmp768, float 0.000000e+00, i32 3
@@ -1031,11 +1031,11 @@ IF173: ; preds = %ENDIF169
%one.sub.ac.i62 = fmul float %one.sub.a.i61, %tmp307
%mul.i63 = fmul float %result.i160, %tmp307
%result.i64 = fadd float %mul.i63, %one.sub.ac.i62
- %tmp793 = insertelement <4 x float> undef, float %tmp333, i32 0
+ %tmp793 = insertelement <4 x float> poison, float %tmp333, i32 0
%tmp794 = insertelement <4 x float> %tmp793, float %tmp334, i32 1
%tmp795 = insertelement <4 x float> %tmp794, float %tmp335, i32 2
%tmp796 = insertelement <4 x float> %tmp795, float 0.000000e+00, i32 3
- %tmp797 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp797 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp798 = insertelement <4 x float> %tmp797, float %tmp65, i32 1
%tmp799 = insertelement <4 x float> %tmp798, float %tmp67, i32 2
%tmp800 = insertelement <4 x float> %tmp799, float 0.000000e+00, i32 3
@@ -1045,11 +1045,11 @@ IF173: ; preds = %ENDIF169
%tmp804 = fmul float %tmp8, %tmp803
%tmp805 = fmul float %tmp13, %tmp803
%tmp806 = fmul float %tmp18, %tmp803
- %tmp807 = insertelement <4 x float> undef, float %tmp34, i32 0
+ %tmp807 = insertelement <4 x float> poison, float %tmp34, i32 0
%tmp808 = insertelement <4 x float> %tmp807, float %tmp35, i32 1
%tmp809 = insertelement <4 x float> %tmp808, float %tmp36, i32 2
%tmp810 = insertelement <4 x float> %tmp809, float 0.000000e+00, i32 3
- %tmp811 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp811 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp812 = insertelement <4 x float> %tmp811, float %tmp65, i32 1
%tmp813 = insertelement <4 x float> %tmp812, float %tmp67, i32 2
%tmp814 = insertelement <4 x float> %tmp813, float 0.000000e+00, i32 3
@@ -1098,11 +1098,11 @@ IF176: ; preds = %ENDIF172
%one.sub.ac.i46 = fmul float %one.sub.a.i45, %tmp307
%mul.i47 = fmul float %result.i160, %tmp307
%result.i48 = fadd float %mul.i47, %one.sub.ac.i46
- %tmp831 = insertelement <4 x float> undef, float %tmp333, i32 0
+ %tmp831 = insertelement <4 x float> poison, float %tmp333, i32 0
%tmp832 = insertelement <4 x float> %tmp831, float %tmp334, i32 1
%tmp833 = insertelement <4 x float> %tmp832, float %tmp335, i32 2
%tmp834 = insertelement <4 x float> %tmp833, float 0.000000e+00, i32 3
- %tmp835 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp835 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp836 = insertelement <4 x float> %tmp835, float %tmp65, i32 1
%tmp837 = insertelement <4 x float> %tmp836, float %tmp67, i32 2
%tmp838 = insertelement <4 x float> %tmp837, float 0.000000e+00, i32 3
@@ -1112,11 +1112,11 @@ IF176: ; preds = %ENDIF172
%tmp842 = fmul float %tmp8, %tmp841
%tmp843 = fmul float %tmp13, %tmp841
%tmp844 = fmul float %tmp18, %tmp841
- %tmp845 = insertelement <4 x float> undef, float %tmp34, i32 0
+ %tmp845 = insertelement <4 x float> poison, float %tmp34, i32 0
%tmp846 = insertelement <4 x float> %tmp845, float %tmp35, i32 1
%tmp847 = insertelement <4 x float> %tmp846, float %tmp36, i32 2
%tmp848 = insertelement <4 x float> %tmp847, float 0.000000e+00, i32 3
- %tmp849 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp849 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp850 = insertelement <4 x float> %tmp849, float %tmp65, i32 1
%tmp851 = insertelement <4 x float> %tmp850, float %tmp67, i32 2
%tmp852 = insertelement <4 x float> %tmp851, float 0.000000e+00, i32 3
@@ -1149,11 +1149,11 @@ IF179: ; preds = %ENDIF175
%tmp866 = fadd float %result.i, 1.000000e+00
%tmp867 = fadd float %result.i, 1.000000e+00
%tmp868 = fadd float %result.i, 1.000000e+00
- %tmp869 = insertelement <4 x float> undef, float %tmp43, i32 0
+ %tmp869 = insertelement <4 x float> poison, float %tmp43, i32 0
%tmp870 = insertelement <4 x float> %tmp869, float %tmp44, i32 1
%tmp871 = insertelement <4 x float> %tmp870, float %tmp45, i32 2
%tmp872 = insertelement <4 x float> %tmp871, float 0.000000e+00, i32 3
- %tmp873 = insertelement <4 x float> undef, float %tmp43, i32 0
+ %tmp873 = insertelement <4 x float> poison, float %tmp43, i32 0
%tmp874 = insertelement <4 x float> %tmp873, float %tmp44, i32 1
%tmp875 = insertelement <4 x float> %tmp874, float %tmp45, i32 2
%tmp876 = insertelement <4 x float> %tmp875, float 0.000000e+00, i32 3
@@ -1209,11 +1209,11 @@ IF179: ; preds = %ENDIF175
%one.sub.ac.i14 = fmul float %one.sub.a.i13, %temp87.5
%mul.i15 = fmul float %result.i32, %temp87.5
%result.i16 = fadd float %mul.i15, %one.sub.ac.i14
- %tmp896 = insertelement <4 x float> undef, float %tmp333, i32 0
+ %tmp896 = insertelement <4 x float> poison, float %tmp333, i32 0
%tmp897 = insertelement <4 x float> %tmp896, float %tmp334, i32 1
%tmp898 = insertelement <4 x float> %tmp897, float %tmp335, i32 2
%tmp899 = insertelement <4 x float> %tmp898, float 0.000000e+00, i32 3
- %tmp900 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp900 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp901 = insertelement <4 x float> %tmp900, float %tmp65, i32 1
%tmp902 = insertelement <4 x float> %tmp901, float %tmp67, i32 2
%tmp903 = insertelement <4 x float> %tmp902, float 0.000000e+00, i32 3
@@ -1223,11 +1223,11 @@ IF179: ; preds = %ENDIF175
%tmp907 = fmul float %tmp8, %tmp906
%tmp908 = fmul float %tmp13, %tmp906
%tmp909 = fmul float %tmp18, %tmp906
- %tmp910 = insertelement <4 x float> undef, float %tmp34, i32 0
+ %tmp910 = insertelement <4 x float> poison, float %tmp34, i32 0
%tmp911 = insertelement <4 x float> %tmp910, float %tmp35, i32 1
%tmp912 = insertelement <4 x float> %tmp911, float %tmp36, i32 2
%tmp913 = insertelement <4 x float> %tmp912, float 0.000000e+00, i32 3
- %tmp914 = insertelement <4 x float> undef, float %tmp63, i32 0
+ %tmp914 = insertelement <4 x float> poison, float %tmp63, i32 0
%tmp915 = insertelement <4 x float> %tmp914, float %tmp65, i32 1
%tmp916 = insertelement <4 x float> %tmp915, float %tmp67, i32 2
%tmp917 = insertelement <4 x float> %tmp916, float 0.000000e+00, i32 3
@@ -1289,7 +1289,7 @@ ENDIF178: ; preds = %IF179, %ENDIF175
%one.sub.ac.i2 = fmul float %one.sub.a.i1, %tmp51
%mul.i3 = fmul float %tmp930, %tmp51
%result.i4 = fadd float %mul.i3, %one.sub.ac.i2
- %tmp953 = insertelement <4 x float> undef, float %result.i12, i32 0
+ %tmp953 = insertelement <4 x float> poison, float %result.i12, i32 0
%tmp954 = insertelement <4 x float> %tmp953, float %result.i8, i32 1
%tmp955 = insertelement <4 x float> %tmp954, float %result.i4, i32 2
%tmp956 = insertelement <4 x float> %tmp955, float %tmp931, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll b/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
index 831017fae3111..8a24845980e1a 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
+++ b/llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll
@@ -48,9 +48,9 @@ bb1789: ; preds = %bb1750
%i1883 = shufflevector <3 x i32> %i1882, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
%i1884 = bitcast <4 x i32> %i1883 to <4 x float>
%i1885 = shufflevector <4 x float> %i1884, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
- %i1886 = insertelement <3 x i32> undef, i32 %i1819, i64 0
+ %i1886 = insertelement <3 x i32> poison, i32 %i1819, i64 0
%i1887 = bitcast <3 x i32> %i1886 to <3 x float>
- %i1888 = insertelement <3 x i32> undef, i32 %i1801, i64 0
+ %i1888 = insertelement <3 x i32> poison, i32 %i1801, i64 0
%i1889 = bitcast <3 x i32> %i1888 to <3 x float>
%i1890 = fmul reassoc nnan nsz arcp contract afn <3 x float> %i1887, %i1889
%i1891 = shufflevector <3 x float> %i1890, <3 x float> poison, <3 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll b/llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
index 2acd2355965a5..99166aed6b215 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
+++ b/llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
@@ -15,15 +15,15 @@ entry:
%tmp2 = getelementptr inbounds double, ptr addrspace(1) %tmp1, i64 undef
%tmp4 = load <3 x double>, ptr addrspace(1) %tmp2, align 8, !tbaa !6
%tmp5 = extractelement <3 x double> %tmp4, i32 1
- %tmp6 = insertelement <3 x double> undef, double %tmp5, i32 1
- %tmp7 = insertelement <3 x double> %tmp6, double undef, i32 2
+ %tmp6 = insertelement <3 x double> poison, double %tmp5, i32 1
+ %tmp7 = insertelement <3 x double> %tmp6, double poison, i32 2
%tmp8 = load <3 x double>, ptr addrspace(1) undef, align 8, !tbaa !6
%tmp9 = extractelement <3 x double> %tmp8, i32 2
- %tmp10 = insertelement <3 x double> undef, double %tmp9, i32 2
+ %tmp10 = insertelement <3 x double> poison, double %tmp9, i32 2
%tmp11 = fcmp olt <3 x double> %tmp10, %tmp7
%tmp12 = select <3 x i1> %tmp11, <3 x double> zeroinitializer, <3 x double> <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>
%tmp13 = extractelement <3 x double> %tmp12, i64 1
- %tmp14 = insertelement <2 x double> undef, double %tmp13, i32 1
+ %tmp14 = insertelement <2 x double> poison, double %tmp13, i32 1
store <2 x double> %tmp14, ptr addrspace(1) undef, align 8, !tbaa !6
ret void
}
@@ -42,12 +42,12 @@ entry:
%tmp2 = getelementptr inbounds double, ptr addrspace(1) %tmp1, i64 undef
%tmp4 = load <3 x double>, ptr addrspace(1) %tmp2, align 8, !tbaa !6
%tmp5 = extractelement <3 x double> %tmp4, i32 1
- %tmp6 = insertelement <3 x double> undef, double %tmp5, i32 1
- %tmp7 = insertelement <3 x double> %tmp6, double undef, i32 2
+ %tmp6 = insertelement <3 x double> poison, double %tmp5, i32 1
+ %tmp7 = insertelement <3 x double> %tmp6, double poison, i32 2
%tmp8 = load <3 x double>, ptr addrspace(1) undef, align 8, !tbaa !6
%tmp9 = extractelement <3 x double> %tmp8, i32 1
- %tmp10 = insertelement <3 x double> undef, double %tmp9, i32 1
- %tmp11 = insertelement <3 x double> %tmp10, double undef, i32 2
+ %tmp10 = insertelement <3 x double> poison, double %tmp9, i32 1
+ %tmp11 = insertelement <3 x double> %tmp10, double poison, i32 2
%tmp12 = fcmp olt <3 x double> %tmp11, %tmp7
%tmp13 = select <3 x i1> %tmp12, <3 x double> zeroinitializer, <3 x double> <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>
%tmp14 = extractelement <3 x double> %tmp13, i64 2
diff --git a/llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll b/llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll
index efe8f9303e2dd..f70b3fd9548ae 100644
--- a/llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll
+++ b/llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll
@@ -15,7 +15,7 @@ bb1:
%tmp2 = phi half [ 0xH0000, %bb ], [ %tmp8, %bb1 ]
%tmp3 = load volatile half, ptr null, align 536870912
%tmp4 = bitcast half %tmp3 to i16
- %tmp5 = insertelement <2 x i16> <i16 0, i16 undef>, i16 %tmp4, i32 1
+ %tmp5 = insertelement <2 x i16> <i16 0, i16 poison>, i16 %tmp4, i32 1
store volatile half %tmp2, ptr %arg, align 2
%tmp7 = bitcast <2 x i16> %tmp to <2 x half>
%tmp8 = extractelement <2 x half> %tmp7, i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll b/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
index 46b2f82d9de2a..f369b24e0f1b3 100644
--- a/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
+++ b/llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
@@ -20,7 +20,7 @@ define void @undef_lo_v2i16(i16 %arg0) {
; GFX8-NEXT: ; use v0
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
- %undef.lo = insertelement <2 x i16> undef, i16 %arg0, i32 1
+ %undef.lo = insertelement <2 x i16> poison, i16 %arg0, i32 1
call void asm sideeffect "; use $0", "v"(<2 x i16> %undef.lo);
ret void
}
@@ -43,7 +43,7 @@ define void @undef_lo_v2f16(half %arg0) {
; GFX8-NEXT: ; use v0
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
- %undef.lo = insertelement <2 x half> undef, half %arg0, i32 1
+ %undef.lo = insertelement <2 x half> poison, half %arg0, i32 1
call void asm sideeffect "; use $0", "v"(<2 x half> %undef.lo);
ret void
}
@@ -69,7 +69,7 @@ define void @undef_lo_op_v2f16(half %arg0) {
; GFX8-NEXT: ; use v0
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
- %undef.lo = insertelement <2 x half> undef, half %arg0, i32 1
+ %undef.lo = insertelement <2 x half> poison, half %arg0, i32 1
%op = fadd <2 x half> %undef.lo, <half 1.0, half 1.0>
call void asm sideeffect "; use $0", "v"(<2 x half> %op);
ret void
@@ -96,7 +96,7 @@ define void @undef_lo_op_v2i16(i16 %arg0) {
; GFX8-NEXT: ; use v0
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
- %undef.lo = insertelement <2 x i16> undef, i16 %arg0, i32 1
+ %undef.lo = insertelement <2 x i16> poison, i16 %arg0, i32 1
%op = add <2 x i16> %undef.lo, <i16 99, i16 99>
call void asm sideeffect "; use $0", "v"(<2 x i16> %op);
ret void
@@ -120,7 +120,7 @@ define void @undef_lo3_v4i16(i16 %arg0) {
; GFX8-NEXT: ; use v[0:1]
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
- %undef.lo = insertelement <4 x i16> undef, i16 %arg0, i32 1
+ %undef.lo = insertelement <4 x i16> poison, i16 %arg0, i32 1
call void asm sideeffect "; use $0", "v"(<4 x i16> %undef.lo);
ret void
}
@@ -143,7 +143,7 @@ define void @undef_lo3_v4f16(half %arg0) {
; GFX8-NEXT: ; use v[0:1]
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
- %undef.lo = insertelement <4 x half> undef, half %arg0, i32 1
+ %undef.lo = insertelement <4 x half> poison, half %arg0, i32 1
call void asm sideeffect "; use $0", "v"(<4 x half> %undef.lo);
ret void
}
@@ -214,7 +214,7 @@ define void @undef_hi_v2i16(i16 %arg0) {
; GFX8-NEXT: ; use v0
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
- %undef.hi = insertelement <2 x i16> undef, i16 %arg0, i32 0
+ %undef.hi = insertelement <2 x i16> poison, i16 %arg0, i32 0
call void asm sideeffect "; use $0", "v"(<2 x i16> %undef.hi);
ret void
}
@@ -235,7 +235,7 @@ define void @undef_hi_v2f16(half %arg0) {
; GFX8-NEXT: ; use v0
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
- %undef.hi = insertelement <2 x half> undef, half %arg0, i32 0
+ %undef.hi = insertelement <2 x half> poison, half %arg0, i32 0
call void asm sideeffect "; use $0", "v"(<2 x half> %undef.hi);
ret void
}
@@ -259,7 +259,7 @@ define void @undef_hi_op_v2f16(half %arg0) {
; GFX8-NEXT: ; use v0
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
- %undef.hi = insertelement <2 x half> undef, half %arg0, i32 0
+ %undef.hi = insertelement <2 x half> poison, half %arg0, i32 0
%op = fadd <2 x half> %undef.hi, <half 1.0, half 1.0>
call void asm sideeffect "; use $0", "v"(<2 x half> %op);
ret void
@@ -284,7 +284,7 @@ define void @undef_hi_op_v2i16(i16 %arg0) {
; GFX8-NEXT: ; use v0
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
- %undef.hi = insertelement <2 x i16> undef, i16 %arg0, i32 0
+ %undef.hi = insertelement <2 x i16> poison, i16 %arg0, i32 0
%op = add <2 x i16> %undef.hi, <i16 99, i16 99>
call void asm sideeffect "; use $0", "v"(<2 x i16> %op);
ret void
@@ -306,7 +306,7 @@ define void @undef_hi3_v4i16(i16 %arg0) {
; GFX8-NEXT: ; use v[0:1]
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
- %undef.hi = insertelement <4 x i16> undef, i16 %arg0, i32 0
+ %undef.hi = insertelement <4 x i16> poison, i16 %arg0, i32 0
call void asm sideeffect "; use $0", "v"(<4 x i16> %undef.hi);
ret void
}
@@ -327,7 +327,7 @@ define void @undef_hi3_v4f16(half %arg0) {
; GFX8-NEXT: ; use v[0:1]
; GFX8-NEXT: ;;#ASMEND
; GFX8-NEXT: s_setpc_b64 s[30:31]
- %undef.hi = insertelement <4 x half> undef, half %arg0, i32 0
+ %undef.hi = insertelement <4 x half> poison, half %arg0, i32 0
call void asm sideeffect "; use $0", "v"(<4 x half> %undef.hi);
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/build_vector-r600.ll b/llvm/test/CodeGen/AMDGPU/build_vector-r600.ll
index 2abcbbcdd1bc6..df26fd8430774 100644
--- a/llvm/test/CodeGen/AMDGPU/build_vector-r600.ll
+++ b/llvm/test/CodeGen/AMDGPU/build_vector-r600.ll
@@ -72,7 +72,7 @@ define amdgpu_kernel void @build_vector_v2i16_trunc (ptr addrspace(1) %out, i32
; R600-NEXT: 327680(4.591775e-40), 2(2.802597e-45)
%srl = lshr i32 %a, 16
%trunc = trunc i32 %srl to i16
- %ins.0 = insertelement <2 x i16> undef, i16 %trunc, i32 0
+ %ins.0 = insertelement <2 x i16> poison, i16 %trunc, i32 0
%ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 1
store <2 x i16> %ins.1, ptr addrspace(1) %out
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/build_vector.ll b/llvm/test/CodeGen/AMDGPU/build_vector.ll
index b79984f41114e..7208eaeff8eb1 100644
--- a/llvm/test/CodeGen/AMDGPU/build_vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/build_vector.ll
@@ -245,7 +245,7 @@ define amdgpu_kernel void @build_vector_v2i16_trunc (ptr addrspace(1) %out, i32
; GFX942-NEXT: s_endpgm
%srl = lshr i32 %a, 16
%trunc = trunc i32 %srl to i16
- %ins.0 = insertelement <2 x i16> undef, i16 %trunc, i32 0
+ %ins.0 = insertelement <2 x i16> poison, i16 %trunc, i32 0
%ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 1
store <2 x i16> %ins.1, ptr addrspace(1) %out
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/bypass-div.ll b/llvm/test/CodeGen/AMDGPU/bypass-div.ll
index 5dde193528aa4..3cf70c42390c2 100644
--- a/llvm/test/CodeGen/AMDGPU/bypass-div.ll
+++ b/llvm/test/CodeGen/AMDGPU/bypass-div.ll
@@ -860,7 +860,7 @@ define <2 x i64> @sdivrem64(i64 %a, i64 %b) {
; GFX9-NEXT: s_setpc_b64 s[30:31]
%d = sdiv i64 %a, %b
%r = srem i64 %a, %b
- %ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0
+ %ins.0 = insertelement <2 x i64> poison, i64 %d, i32 0
%ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1
ret <2 x i64> %ins.1
}
@@ -1012,7 +1012,7 @@ define <2 x i64> @udivrem64(i64 %a, i64 %b) {
; GFX9-NEXT: s_setpc_b64 s[30:31]
%d = udiv i64 %a, %b
%r = urem i64 %a, %b
- %ins.0 = insertelement <2 x i64> undef, i64 %d, i32 0
+ %ins.0 = insertelement <2 x i64> poison, i64 %d, i32 0
%ins.1 = insertelement <2 x i64> %ins.0, i64 %r, i32 1
ret <2 x i64> %ins.1
}
diff --git a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
index b6eca494fe690..55f62058ec7af 100644
--- a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
@@ -72,7 +72,7 @@ bb:
%load_lo = load half, ptr addrspace(5) %gep_lo
%load_hi = load half, ptr addrspace(5) null
- %temp = insertelement <2 x half> undef, half %load_lo, i32 0
+ %temp = insertelement <2 x half> poison, half %load_lo, i32 0
%result = insertelement <2 x half> %temp, half %load_hi, i32 1
ret <2 x half> %result
@@ -133,7 +133,7 @@ bb:
%load_lo = load half, ptr addrspace(5) %base_lo
%load_hi = load half, ptr addrspace(5) %base_hi
- %temp = insertelement <2 x half> undef, half %load_lo, i32 0
+ %temp = insertelement <2 x half> poison, half %load_lo, i32 0
%result = insertelement <2 x half> %temp, half %load_hi, i32 1
ret <2 x half> %result
@@ -197,7 +197,7 @@ bb:
%arith_lo = fadd half %in, 1.0
%load_hi = load half, ptr addrspace(5) %base
- %temp = insertelement <2 x half> undef, half %arith_lo, i32 0
+ %temp = insertelement <2 x half> poison, half %arith_lo, i32 0
%result = insertelement <2 x half> %temp, half %load_hi, i32 1
ret <2 x half> %result
@@ -238,7 +238,7 @@ bb:
%load_lo = load half, ptr addrspace(3) %gep_lo
%load_hi = load half, ptr addrspace(3) null
- %temp = insertelement <2 x half> undef, half %load_lo, i32 0
+ %temp = insertelement <2 x half> poison, half %load_lo, i32 0
%result = insertelement <2 x half> %temp, half %load_hi, i32 1
ret <2 x half> %result
@@ -275,7 +275,7 @@ bb:
%load_lo = load half, ptr addrspace(3) %base_lo
%load_hi = load half, ptr addrspace(3) %base_hi
- %temp = insertelement <2 x half> undef, half %load_lo, i32 0
+ %temp = insertelement <2 x half> poison, half %load_lo, i32 0
%result = insertelement <2 x half> %temp, half %load_hi, i32 1
ret <2 x half> %result
@@ -334,7 +334,7 @@ bb:
%load_lo = load half, ptr addrspace(1) %gep_lo
%load_hi = load half, ptr addrspace(1) null
- %temp = insertelement <2 x half> undef, half %load_lo, i32 0
+ %temp = insertelement <2 x half> poison, half %load_lo, i32 0
%result = insertelement <2 x half> %temp, half %load_hi, i32 1
ret <2 x half> %result
@@ -377,7 +377,7 @@ bb:
%load_lo = load half, ptr addrspace(1) %base_lo
%load_hi = load half, ptr addrspace(1) %base_hi
- %temp = insertelement <2 x half> undef, half %load_lo, i32 0
+ %temp = insertelement <2 x half> poison, half %load_lo, i32 0
%result = insertelement <2 x half> %temp, half %load_hi, i32 1
ret <2 x half> %result
@@ -440,7 +440,7 @@ bb:
%load_lo = load half, ptr %gep_lo
%load_hi = load half, ptr null
- %temp = insertelement <2 x half> undef, half %load_lo, i32 0
+ %temp = insertelement <2 x half> poison, half %load_lo, i32 0
%result = insertelement <2 x half> %temp, half %load_hi, i32 1
ret <2 x half> %result
@@ -486,7 +486,7 @@ bb:
%load_lo = load half, ptr %base_lo
%load_hi = load half, ptr %base_hi
- %temp = insertelement <2 x half> undef, half %load_lo, i32 0
+ %temp = insertelement <2 x half> poison, half %load_lo, i32 0
%result = insertelement <2 x half> %temp, half %load_hi, i32 1
ret <2 x half> %result
@@ -740,7 +740,7 @@ bb:
%gep_lo = getelementptr inbounds i16, ptr addrspace(3) %ptr, i64 1
%load_lo = load i16, ptr addrspace(3) %gep_lo
%load_hi = load i16, ptr addrspace(3) %ptr
- %to.hi = insertelement <2 x i16> undef, i16 %load_hi, i32 1
+ %to.hi = insertelement <2 x i16> poison, i16 %load_hi, i32 1
%op.hi = add <2 x i16> %to.hi, <i16 12, i16 12>
%result = insertelement <2 x i16> %op.hi, i16 %load_lo, i32 0
ret <2 x i16> %result
@@ -794,7 +794,7 @@ bb:
%gep_lo = getelementptr inbounds i16, ptr addrspace(3) %ptr, i64 1
%load_lo = load volatile i16, ptr addrspace(3) %gep_lo
%load_hi = load volatile i16, ptr addrspace(3) %ptr
- %to.hi = insertelement <2 x i16> undef, i16 %load_hi, i32 1
+ %to.hi = insertelement <2 x i16> poison, i16 %load_hi, i32 1
%op.hi = add <2 x i16> %to.hi, <i16 12, i16 12>
%result = insertelement <2 x i16> %op.hi, i16 %load_lo, i32 0
ret <2 x i16> %result
@@ -859,7 +859,7 @@ bb:
%gep_lo = getelementptr inbounds i16, ptr addrspace(5) %ptr, i64 1
%load_lo = load i16, ptr addrspace(5) %gep_lo
%load_hi = load i16, ptr addrspace(5) %ptr
- %to.hi = insertelement <2 x i16> undef, i16 %load_hi, i32 1
+ %to.hi = insertelement <2 x i16> poison, i16 %load_hi, i32 1
%op.hi = add <2 x i16> %to.hi, <i16 12, i16 12>
%result = insertelement <2 x i16> %op.hi, i16 %load_lo, i32 0
ret <2 x i16> %result
@@ -929,7 +929,7 @@ bb:
%gep_lo = getelementptr inbounds i16, ptr addrspace(1) %ptr, i64 1
%load_lo = load volatile i16, ptr addrspace(1) %gep_lo
%load_hi = load volatile i16, ptr addrspace(1) %ptr
- %to.hi = insertelement <2 x i16> undef, i16 %load_hi, i32 1
+ %to.hi = insertelement <2 x i16> poison, i16 %load_hi, i32 1
%op.hi = add <2 x i16> %to.hi, <i16 12, i16 12>
%result = insertelement <2 x i16> %op.hi, i16 %load_lo, i32 0
ret <2 x i16> %result
@@ -1004,7 +1004,7 @@ bb:
%gep_lo = getelementptr inbounds i16, ptr addrspace(0) %ptr, i64 1
%load_lo = load volatile i16, ptr addrspace(0) %gep_lo
%load_hi = load volatile i16, ptr addrspace(0) %ptr
- %to.hi = insertelement <2 x i16> undef, i16 %load_hi, i32 1
+ %to.hi = insertelement <2 x i16> poison, i16 %load_hi, i32 1
%op.hi = add <2 x i16> %to.hi, <i16 12, i16 12>
%result = insertelement <2 x i16> %op.hi, i16 %load_lo, i32 0
ret <2 x i16> %result
@@ -1073,7 +1073,7 @@ bb:
store i16 123, ptr addrspace(3) %may.alias
%load_lo = load i16, ptr addrspace(3) %gep_lo
- %to.hi = insertelement <2 x i16> undef, i16 %load_hi, i32 1
+ %to.hi = insertelement <2 x i16> poison, i16 %load_hi, i32 1
%result = insertelement <2 x i16> %to.hi, i16 %load_lo, i32 0
ret <2 x i16> %result
}
diff --git a/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll b/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
index 12057caec6e84..61830f18ad7a7 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
+++ b/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll
@@ -26,7 +26,7 @@ loop:
%v3 = phi float [0.0, %entry], [%fma.3, %loop]
; Try to get the 0 constant to get coalesced into a wide register
- %blup = insertelement <4 x float> undef, float %v0, i32 0
+ %blup = insertelement <4 x float> poison, float %v0, i32 0
store <4 x float> %blup, ptr addrspace(1) %out
%load = load <4 x float>, ptr addrspace(1) %in
@@ -48,7 +48,7 @@ exit:
%ev1 = phi float [0.0, %entry], [%fma.1, %loop]
%ev2 = phi float [0.0, %entry], [%fma.2, %loop]
%ev3 = phi float [0.0, %entry], [%fma.3, %loop]
- %dst.0 = insertelement <4 x float> undef, float %ev0, i32 0
+ %dst.0 = insertelement <4 x float> poison, float %ev0, i32 0
%dst.1 = insertelement <4 x float> %dst.0, float %ev1, i32 1
%dst.2 = insertelement <4 x float> %dst.1, float %ev2, i32 2
%dst.3 = insertelement <4 x float> %dst.2, float %ev3, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
index a47ecb2c5d7f2..c8a4f2d2e6b7b 100644
--- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
+++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
@@ -1365,7 +1365,7 @@ bb4: ; preds = %bb2
br i1 %tmp7, label %bb8, label %Flow
bb8: ; preds = %bb4
- %tmp9 = insertelement <4 x float> undef, float 0.0, i32 1
+ %tmp9 = insertelement <4 x float> poison, float 0.0, i32 1
br label %Flow
Flow: ; preds = %bb8, %bb4
diff --git a/llvm/test/CodeGen/AMDGPU/complex-folding.ll b/llvm/test/CodeGen/AMDGPU/complex-folding.ll
index cf19b92e3fd8c..3d124e8cb7f4a 100644
--- a/llvm/test/CodeGen/AMDGPU/complex-folding.ll
+++ b/llvm/test/CodeGen/AMDGPU/complex-folding.ll
@@ -8,7 +8,7 @@ entry:
%1 = call float @fabsf(float %0)
%2 = fptoui float %1 to i32
%3 = bitcast i32 %2 to float
- %4 = insertelement <4 x float> undef, float %3, i32 0
+ %4 = insertelement <4 x float> poison, float %3, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %4, i32 0, i32 0)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/cube.ll b/llvm/test/CodeGen/AMDGPU/cube.ll
index 49d8276eda418..72711df2ad445 100644
--- a/llvm/test/CodeGen/AMDGPU/cube.ll
+++ b/llvm/test/CodeGen/AMDGPU/cube.ll
@@ -18,7 +18,7 @@ define amdgpu_kernel void @cube(ptr addrspace(1) %out, float %a, float %b, float
%cubetc = call float @llvm.amdgcn.cubetc(float %a, float %b, float %c)
%cubema = call float @llvm.amdgcn.cubema(float %a, float %b, float %c)
- %vec0 = insertelement <4 x float> undef, float %cubeid, i32 0
+ %vec0 = insertelement <4 x float> poison, float %cubeid, i32 0
%vec1 = insertelement <4 x float> %vec0, float %cubesc, i32 1
%vec2 = insertelement <4 x float> %vec1, float %cubetc, i32 2
%vec3 = insertelement <4 x float> %vec2, float %cubema, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index fec020a296b9b..5a301aaacb6f2 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -456,7 +456,7 @@ define <4 x float> @v_uitofp_unpack_i32_to_v4f32(i32 %arg0) nounwind {
%mask.lshr.24 = and i32 %lshr.24, 255
%cvt3 = uitofp i32 %mask.lshr.24 to float
- %ins.0 = insertelement <4 x float> undef, float %cvt0, i32 0
+ %ins.0 = insertelement <4 x float> poison, float %cvt0, i32 0
%ins.1 = insertelement <4 x float> %ins.0, float %cvt1, i32 1
%ins.2 = insertelement <4 x float> %ins.1, float %cvt2, i32 2
%ins.3 = insertelement <4 x float> %ins.2, float %cvt3, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll b/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
index 7d14a5b811b7f..e66fdce283026 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll
@@ -16,12 +16,12 @@ define amdgpu_ps void @main(i32 %in1, i32 inreg %arg) local_unnamed_addr {
br i1 %cond, label %bb12, label %bb
bb:
- %__llpc_global_proxy_r5.12.vec.insert = insertelement <4 x i32> undef, i32 %in1, i32 3
+ %__llpc_global_proxy_r5.12.vec.insert = insertelement <4 x i32> poison, i32 %in1, i32 3
%tmp3 = shufflevector <4 x i32> %__llpc_global_proxy_r5.12.vec.insert, <4 x i32> undef, <3 x i32> <i32 undef, i32 undef, i32 1>
%tmp4 = bitcast <3 x i32> %tmp3 to <3 x float>
%a2.i123 = extractelement <3 x float> %tmp4, i32 2
%tmp5 = bitcast float %a2.i123 to i32
- %__llpc_global_proxy_r2.0.vec.insert196 = insertelement <4 x i32> undef, i32 %tmp5, i32 0
+ %__llpc_global_proxy_r2.0.vec.insert196 = insertelement <4 x i32> poison, i32 %tmp5, i32 0
br label %bb12
bb12:
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombiner-bug-illegal-vec4-int-to-fp.ll b/llvm/test/CodeGen/AMDGPU/dagcombiner-bug-illegal-vec4-int-to-fp.ll
index 9333c7a5d43dc..ccd497670a3f0 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombiner-bug-illegal-vec4-int-to-fp.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombiner-bug-illegal-vec4-int-to-fp.ll
@@ -15,7 +15,7 @@ entry:
%ptr = getelementptr i32, ptr addrspace(1) %in, i32 1
%sint = load i32, ptr addrspace(1) %in
%conv = sitofp i32 %sint to float
- %0 = insertelement <4 x float> undef, float %conv, i32 0
+ %0 = insertelement <4 x float> poison, float %conv, i32 0
%splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
store <4 x float> %splat, ptr addrspace(1) %out
ret void
@@ -29,7 +29,7 @@ entry:
%ptr = getelementptr i32, ptr addrspace(1) %in, i32 1
%uint = load i32, ptr addrspace(1) %in
%conv = uitofp i32 %uint to float
- %0 = insertelement <4 x float> undef, float %conv, i32 0
+ %0 = insertelement <4 x float> poison, float %conv, i32 0
%splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
store <4 x float> %splat, ptr addrspace(1) %out
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll b/llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
index d3e42260cd5cb..e9d109b4aa1a9 100644
--- a/llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
+++ b/llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll
@@ -14,7 +14,7 @@ entry:
sw.bb4:
%x = load i64, ptr addrspace(1) undef, align 8
%c = sitofp i64 %x to float
- %v = insertelement <2 x float> <float undef, float 0.000000e+00>, float %c, i32 0
+ %v = insertelement <2 x float> <float poison, float 0.000000e+00>, float %c, i32 0
br label %foo.exit
sw.bb10:
diff --git a/llvm/test/CodeGen/AMDGPU/debug-value.ll b/llvm/test/CodeGen/AMDGPU/debug-value.ll
index 127b23ed3bb23..755f517156a7a 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-value.ll
+++ b/llvm/test/CodeGen/AMDGPU/debug-value.ll
@@ -29,8 +29,8 @@ bb21: ; preds = %bb
br label %bb28
bb25: ; preds = %bb
- %tmp26 = insertelement <4 x float> undef, float 0.000000e+00, i32 1
- %tmp27 = insertelement <4 x float> %tmp26, float undef, i32 2
+ %tmp26 = insertelement <4 x float> poison, float 0.000000e+00, i32 1
+ %tmp27 = insertelement <4 x float> %tmp26, float poison, i32 2
br label %bb28
bb28: ; preds = %bb25, %bb21
@@ -52,7 +52,7 @@ bb28: ; preds = %bb25, %bb21
%tmp44 = fsub float %tmp43, undef
%tmp45 = fadd float undef, undef
%tmp46 = fdiv float %tmp44, %tmp45
- %tmp47 = insertelement <4 x float> undef, float %tmp46, i32 0
+ %tmp47 = insertelement <4 x float> poison, float %tmp46, i32 0
%tmp48 = shufflevector <4 x float> %tmp47, <4 x float> undef, <4 x i32> zeroinitializer
%tmp49 = fsub <4 x float> %tmp48, %tmp40
%tmp50 = extractelement <4 x float> %tmp41, i32 1
@@ -70,7 +70,7 @@ bb28: ; preds = %bb25, %bb21
; CHECK-NOT: ;DEBUG_VALUE:
call void @llvm.dbg.value(metadata <4 x float> %tmp29, metadata !3, metadata !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)) #2, !dbg !5
%tmp59 = bitcast i64 %tmp35 to <2 x float>
- %tmp60 = insertelement <2 x float> undef, float %tmp58, i32 0
+ %tmp60 = insertelement <2 x float> poison, float %tmp58, i32 0
%tmp61 = shufflevector <2 x float> %tmp60, <2 x float> undef, <2 x i32> zeroinitializer
%tmp62 = fmul <2 x float> %tmp61, undef
%tmp63 = fsub <2 x float> %tmp62, %tmp59
diff --git a/llvm/test/CodeGen/AMDGPU/debug-value2.ll b/llvm/test/CodeGen/AMDGPU/debug-value2.ll
index b09d540dd6d7b..bd27100a27cfc 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-value2.ll
+++ b/llvm/test/CodeGen/AMDGPU/debug-value2.ll
@@ -25,7 +25,7 @@ entry:
%tmp1 = load <4 x float>, ptr addrspace(1) %m_angularMotion, align 16
%m_scaleMotion = getelementptr inbounds %struct.ShapeData, ptr addrspace(1) %call, i64 0, i32 4
%tmp2 = load <4 x float>, ptr addrspace(1) %m_scaleMotion, align 16
- %splat.splatinsert = insertelement <4 x float> undef, float %time, i32 0
+ %splat.splatinsert = insertelement <4 x float> poison, float %time, i32 0
%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
%tmp3 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %tmp2, <4 x float> %splat.splat, <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>)
%tmp4 = load <4 x float>, ptr addrspace(1) %call, align 16
@@ -36,7 +36,7 @@ entry:
%mul = fmul <4 x float> %tmp6, %v
%tmp7 = extractelement <4 x float> %tmp5, i64 0
%sub.i.i = fsub float -0.000000e+00, %tmp7
- %vecinit.i.i = insertelement <4 x float> undef, float %sub.i.i, i32 0
+ %vecinit.i.i = insertelement <4 x float> poison, float %sub.i.i, i32 0
%tmp8 = extractelement <4 x float> %tmp5, i64 1
%sub1.i.i = fsub float -0.000000e+00, %tmp8
%vecinit2.i.i = insertelement <4 x float> %vecinit.i.i, float %sub1.i.i, i32 1
@@ -57,7 +57,7 @@ entry:
%tmp20 = fmul float %tmp8, %tmp16
%tmp21 = fsub float -0.000000e+00, %tmp20
%tmp22 = tail call float @llvm.fmuladd.f32(float %tmp7, float %tmp12, float %tmp21)
- %tmp23 = insertelement <4 x float> <float undef, float undef, float undef, float 0.000000e+00>, float %tmp15, i32 0
+ %tmp23 = insertelement <4 x float> <float poison, float poison, float poison, float 0.000000e+00>, float %tmp15, i32 0
%tmp24 = insertelement <4 x float> %tmp23, float %tmp19, i32 1
%tmp25 = insertelement <4 x float> %tmp24, float %tmp22, i32 2
%tmp26 = extractelement <4 x float> %tmp5, i64 3
@@ -91,7 +91,7 @@ entry:
%tmp49 = fmul float %tmp40, %sub.i.i
%tmp50 = fsub float -0.000000e+00, %tmp49
%tmp51 = tail call float @llvm.fmuladd.f32(float %tmp45, float %sub1.i.i, float %tmp50)
- %tmp52 = insertelement <4 x float> <float undef, float undef, float undef, float 0.000000e+00>, float %tmp44, i32 0
+ %tmp52 = insertelement <4 x float> <float poison, float poison, float poison, float 0.000000e+00>, float %tmp44, i32 0
%tmp53 = insertelement <4 x float> %tmp52, float %tmp48, i32 1
%tmp54 = insertelement <4 x float> %tmp53, float %tmp51, i32 2
%splat.splat.i.i = shufflevector <4 x float> %tmp39, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
@@ -169,7 +169,7 @@ bb98: ; preds = %bb96
bb109: ; preds = %bb98
%tmp110 = tail call zeroext i1 @llvm.amdgcn.class.f32(float %tmp103, i32 516)
%tmp111 = sext i1 %tmp110 to i32
- %tmp112 = insertelement <4 x i32> undef, i32 %tmp111, i32 0
+ %tmp112 = insertelement <4 x i32> poison, i32 %tmp111, i32 0
%tmp113 = tail call zeroext i1 @llvm.amdgcn.class.f32(float %tmp102, i32 516)
%tmp114 = sext i1 %tmp113 to i32
%tmp115 = insertelement <4 x i32> %tmp112, i32 %tmp114, i32 1
@@ -184,7 +184,7 @@ bb109: ; preds = %bb98
%tmp124 = bitcast <4 x i32> %tmp123 to <4 x float>
%tmp125 = extractelement <4 x float> %tmp124, i64 0
%tmp126 = tail call float @llvm.copysign.f32(float %tmp125, float %tmp103)
- %tmp127 = insertelement <4 x float> undef, float %tmp126, i32 0
+ %tmp127 = insertelement <4 x float> poison, float %tmp126, i32 0
%tmp128 = extractelement <4 x float> %tmp124, i64 1
%tmp129 = tail call float @llvm.copysign.f32(float %tmp128, float %tmp102)
%tmp130 = insertelement <4 x float> %tmp127, float %tmp129, i32 1
@@ -204,7 +204,7 @@ bb141: ; preds = %bb109, %bb98, %bb96
%tmp142 = phi <4 x float> [ %tmp87, %bb86 ], [ %tmp136, %bb109 ], [ %tmp99, %bb98 ], [ %vecinit3.i.i, %bb96 ]
%tmp143 = phi float [ %tmp95, %bb86 ], [ %tmp140, %bb109 ], [ %tmp107, %bb98 ], [ %tmp84, %bb96 ]
%tmp144 = tail call float @llvm.amdgcn.rsq.f32(float %tmp143)
- %tmp145 = insertelement <4 x float> undef, float %tmp144, i32 0
+ %tmp145 = insertelement <4 x float> poison, float %tmp144, i32 0
%tmp146 = shufflevector <4 x float> %tmp145, <4 x float> undef, <4 x i32> zeroinitializer
%tmp147 = fmul <4 x float> %tmp142, %tmp146
br label %qtSet.exit
@@ -231,7 +231,7 @@ qtSet.exit: ; preds = %bb141, %entry
%tmp151 = tail call float @llvm.fmuladd.f32(float %tmp150, float 0x3FCCCCCCC0000000, float %tmp149)
%tmp152 = extractelement <4 x float> %tmp148, i64 0
%mul.i = fmul float %tmp151, %tmp152
- %tmp153 = insertelement <4 x float> undef, float %mul.i, i64 0
+ %tmp153 = insertelement <4 x float> poison, float %mul.i, i64 0
%tmp154 = extractelement <4 x float> %tmp148, i64 1
%mul2.i = fmul float %tmp151, %tmp154
%tmp155 = insertelement <4 x float> %tmp153, float %mul2.i, i64 1
@@ -258,7 +258,7 @@ qtSet.exit: ; preds = %bb141, %entry
%tmp160 = tail call float @llvm.fmuladd.f32(float %tmp159, float 0x3FCCCCCCC0000000, float %tmp158)
%tmp161 = insertelement <4 x float> %tmp157, float %tmp160, i64 3
%sub.i.i32 = fsub float -0.000000e+00, %mul.i
- %vecinit.i.i33 = insertelement <4 x float> undef, float %sub.i.i32, i32 0
+ %vecinit.i.i33 = insertelement <4 x float> poison, float %sub.i.i32, i32 0
%sub1.i.i34 = fsub float -0.000000e+00, %mul2.i
%vecinit2.i.i35 = insertelement <4 x float> %vecinit.i.i33, float %sub1.i.i34, i32 1
%sub3.i.i36 = fsub float -0.000000e+00, %mul3.i
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
index 4ea553b8aaad0..68ae9854bd7d2 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
@@ -34,9 +34,9 @@ define amdgpu_kernel void @v_abs_i32(ptr addrspace(1) %out, ptr addrspace(1) %sr
; GCN: S_ABS_I32
; GCN: S_ABS_I32
define amdgpu_kernel void @s_abs_v2i32(ptr addrspace(1) %out, <2 x i32> %val) nounwind {
- %z0 = insertelement <2 x i32> undef, i32 0, i32 0
+ %z0 = insertelement <2 x i32> poison, i32 0, i32 0
%z1 = insertelement <2 x i32> %z0, i32 0, i32 1
- %t0 = insertelement <2 x i32> undef, i32 2, i32 0
+ %t0 = insertelement <2 x i32> poison, i32 2, i32 0
%t1 = insertelement <2 x i32> %t0, i32 2, i32 1
%neg = sub <2 x i32> %z1, %val
%cond = icmp sgt <2 x i32> %val, %neg
@@ -52,9 +52,9 @@ define amdgpu_kernel void @s_abs_v2i32(ptr addrspace(1) %out, <2 x i32> %val) no
; GCN: V_MAX_I32_e64
; GCN: V_MAX_I32_e64
define amdgpu_kernel void @v_abs_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %src) nounwind {
- %z0 = insertelement <2 x i32> undef, i32 0, i32 0
+ %z0 = insertelement <2 x i32> poison, i32 0, i32 0
%z1 = insertelement <2 x i32> %z0, i32 0, i32 1
- %t0 = insertelement <2 x i32> undef, i32 2, i32 0
+ %t0 = insertelement <2 x i32> poison, i32 2, i32 0
%t1 = insertelement <2 x i32> %t0, i32 2, i32 1
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.in = getelementptr inbounds <2 x i32>, ptr addrspace(1) %src, i32 %tid
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll b/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
index 142ec2f926e80..ada3f017f45cf 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
@@ -50,7 +50,7 @@ define amdgpu_kernel void @uniform_vec_0_i16(ptr addrspace(1) %out, i16 %a) {
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
- %tmp = insertelement <2 x i16> undef, i16 0, i32 0
+ %tmp = insertelement <2 x i16> poison, i16 0, i32 0
%vec = insertelement <2 x i16> %tmp, i16 %a, i32 1
%val = bitcast <2 x i16> %vec to i32
store i32 %val, ptr addrspace(1) %out, align 4
@@ -81,7 +81,7 @@ define i32 @divergent_vec_0_i16(i16 %a) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
- %tmp = insertelement <2 x i16> undef, i16 0, i32 0
+ %tmp = insertelement <2 x i16> poison, i16 0, i32 0
%vec = insertelement <2 x i16> %tmp, i16 %a, i32 1
%val = bitcast <2 x i16> %vec to i32
ret i32 %val
@@ -133,7 +133,7 @@ define amdgpu_kernel void @uniform_vec_i16_0(ptr addrspace(1) %out, i16 %a) {
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
- %tmp = insertelement <2 x i16> undef, i16 %a, i32 0
+ %tmp = insertelement <2 x i16> poison, i16 %a, i32 0
%vec = insertelement <2 x i16> %tmp, i16 0, i32 1
%val = bitcast <2 x i16> %vec to i32
store i32 %val, ptr addrspace(1) %out, align 4
@@ -164,7 +164,7 @@ define i32 @divergent_vec_i16_0(i16 %a) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
- %tmp = insertelement <2 x i16> undef, i16 %a, i32 0
+ %tmp = insertelement <2 x i16> poison, i16 %a, i32 0
%vec = insertelement <2 x i16> %tmp, i16 0, i32 1
%val = bitcast <2 x i16> %vec to i32
ret i32 %val
@@ -216,7 +216,7 @@ define amdgpu_kernel void @uniform_vec_f16_0(ptr addrspace(1) %out, half %a) {
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
- %tmp = insertelement <2 x half> undef, half %a, i32 0
+ %tmp = insertelement <2 x half> poison, half %a, i32 0
%vec = insertelement <2 x half> %tmp, half 0.0, i32 1
%val = bitcast <2 x half> %vec to float
store float %val, ptr addrspace(1) %out, align 4
@@ -247,7 +247,7 @@ define float @divergent_vec_f16_0(half %a) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
- %tmp = insertelement <2 x half> undef, half %a, i32 0
+ %tmp = insertelement <2 x half> poison, half %a, i32 0
%vec = insertelement <2 x half> %tmp, half 0.0, i32 1
%val = bitcast <2 x half> %vec to float
ret float %val
@@ -311,7 +311,7 @@ define amdgpu_kernel void @uniform_vec_i16_LL(ptr addrspace(4) %in0, ptr addrspa
%val1 = load volatile i32, ptr addrspace(4) %in1
%lo = trunc i32 %val0 to i16
%hi = trunc i32 %val1 to i16
- %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
+ %vec.0 = insertelement <2 x i16> poison, i16 %lo, i32 0
%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
%vec.i32 = bitcast <2 x i16> %vec.1 to i32
call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0
@@ -346,7 +346,7 @@ define i32 @divergent_vec_i16_LL(i16 %a, i16 %b) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-NEXT: s_setpc_b64 s[30:31]
- %tmp = insertelement <2 x i16> undef, i16 %a, i32 0
+ %tmp = insertelement <2 x i16> poison, i16 %a, i32 0
%vec = insertelement <2 x i16> %tmp, i16 %b, i32 1
%val = bitcast <2 x i16> %vec to i32
ret i32 %val
@@ -399,7 +399,7 @@ define amdgpu_kernel void @uniform_vec_i16_LH(ptr addrspace(1) %out, i16 %a, i32
; GFX11-NEXT: s_endpgm
%shift = lshr i32 %b, 16
%tr = trunc i32 %shift to i16
- %tmp = insertelement <2 x i16> undef, i16 %a, i32 0
+ %tmp = insertelement <2 x i16> poison, i16 %a, i32 0
%vec = insertelement <2 x i16> %tmp, i16 %tr, i32 1
%val = bitcast <2 x i16> %vec to i32
store i32 %val, ptr addrspace(1) %out, align 4
@@ -435,7 +435,7 @@ define i32 @divergent_vec_i16_LH(i16 %a, i32 %b) {
; GFX11-NEXT: s_setpc_b64 s[30:31]
%shift = lshr i32 %b, 16
%tr = trunc i32 %shift to i16
- %tmp = insertelement <2 x i16> undef, i16 %a, i32 0
+ %tmp = insertelement <2 x i16> poison, i16 %a, i32 0
%vec = insertelement <2 x i16> %tmp, i16 %tr, i32 1
%val = bitcast <2 x i16> %vec to i32
ret i32 %val
@@ -489,7 +489,7 @@ define amdgpu_kernel void @uniform_vec_i16_HH(ptr addrspace(1) %out, i32 %a, i32
%tr_a = trunc i32 %shift_a to i16
%shift_b = lshr i32 %b, 16
%tr_b = trunc i32 %shift_b to i16
- %tmp = insertelement <2 x i16> undef, i16 %tr_a, i32 0
+ %tmp = insertelement <2 x i16> poison, i16 %tr_a, i32 0
%vec = insertelement <2 x i16> %tmp, i16 %tr_b, i32 1
%val = bitcast <2 x i16> %vec to i32
store i32 %val, ptr addrspace(1) %out, align 4
@@ -527,7 +527,7 @@ define i32 @divergent_vec_i16_HH(i32 %a, i32 %b) {
%tr_a = trunc i32 %shift_a to i16
%shift_b = lshr i32 %b, 16
%tr_b = trunc i32 %shift_b to i16
- %tmp = insertelement <2 x i16> undef, i16 %tr_a, i32 0
+ %tmp = insertelement <2 x i16> poison, i16 %tr_a, i32 0
%vec = insertelement <2 x i16> %tmp, i16 %tr_b, i32 1
%val = bitcast <2 x i16> %vec to i32
ret i32 %val
@@ -593,7 +593,7 @@ define amdgpu_kernel void @uniform_vec_f16_LL(ptr addrspace(4) %in0, ptr addrspa
%hi.i = trunc i32 %val1 to i16
%lo = bitcast i16 %lo.i to half
%hi = bitcast i16 %hi.i to half
- %vec.0 = insertelement <2 x half> undef, half %lo, i32 0
+ %vec.0 = insertelement <2 x half> poison, half %lo, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half %hi, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
@@ -630,7 +630,7 @@ define float @divergent_vec_f16_LL(half %a, half %b) {
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-NEXT: s_setpc_b64 s[30:31]
- %tmp = insertelement <2 x half> undef, half %a, i32 0
+ %tmp = insertelement <2 x half> poison, half %a, i32 0
%vec = insertelement <2 x half> %tmp, half %b, i32 1
%val = bitcast <2 x half> %vec to float
ret float %val
@@ -667,7 +667,7 @@ define <2 x i16> @build_vec_v2i16_undeflo_divergent(ptr addrspace(3) %in) #0 {
; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, ptr addrspace(3) %in
- %build = insertelement <2 x i16> undef, i16 %load, i32 0
+ %build = insertelement <2 x i16> poison, i16 %load, i32 0
ret <2 x i16> %build
}
@@ -723,7 +723,7 @@ define amdgpu_kernel void @build_vec_v2i16_undeflo_uniform(ptr addrspace(3) %in,
; GFX11-NEXT: s_endpgm
entry:
%load = load i16, ptr addrspace(3) %in
- %build = insertelement <2 x i16> undef, i16 %load, i32 0
+ %build = insertelement <2 x i16> poison, i16 %load, i32 0
%result = bitcast <2 x i16> %build to i32
store i32 %result, ptr addrspace(1) %out
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll b/llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll
index 7d75f1947b51a..418023b1501b7 100644
--- a/llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll
@@ -15,7 +15,7 @@ define amdgpu_kernel void @ds_combine_nodep(ptr addrspace(1) %out, ptr addrspace
%load0 = load <3 x float>, ptr addrspace(3) %addr0, align 4
%v0 = extractelement <3 x float> %load0, i32 2
- %tmp1 = insertelement <2 x float> undef, float 1.0, i32 0
+ %tmp1 = insertelement <2 x float> poison, float 1.0, i32 0
%data = insertelement <2 x float> %tmp1, float 2.0, i32 1
%tmp2 = getelementptr float, ptr addrspace(3) %inptr, i32 26
@@ -43,7 +43,7 @@ define amdgpu_kernel void @ds_combine_WAR(ptr addrspace(1) %out, ptr addrspace(3
%load0 = load <3 x float>, ptr addrspace(3) %addr0, align 4
%v0 = extractelement <3 x float> %load0, i32 2
- %tmp1 = insertelement <2 x float> undef, float 1.0, i32 0
+ %tmp1 = insertelement <2 x float> poison, float 1.0, i32 0
%data = insertelement <2 x float> %tmp1, float 2.0, i32 1
%tmp2 = getelementptr float, ptr addrspace(3) %inptr, i32 26
@@ -73,7 +73,7 @@ define amdgpu_kernel void @ds_combine_RAW(ptr addrspace(1) %out, ptr addrspace(3
%load0 = load <3 x float>, ptr addrspace(3) %addr0, align 4
%v0 = extractelement <3 x float> %load0, i32 2
- %tmp1 = insertelement <2 x float> undef, float 1.0, i32 0
+ %tmp1 = insertelement <2 x float> poison, float 1.0, i32 0
%data = insertelement <2 x float> %tmp1, float 2.0, i32 1
%tmp2 = getelementptr float, ptr addrspace(3) %inptr, i32 26
@@ -102,7 +102,7 @@ define amdgpu_kernel void @ds_combine_WAR_RAW(ptr addrspace(1) %out, ptr addrspa
%load0 = load <3 x float>, ptr addrspace(3) %addr0, align 4
%v0 = extractelement <3 x float> %load0, i32 2
- %tmp1 = insertelement <2 x float> undef, float 1.0, i32 0
+ %tmp1 = insertelement <2 x float> poison, float 1.0, i32 0
%data = insertelement <2 x float> %tmp1, float 2.0, i32 1
%tmp2 = getelementptr float, ptr addrspace(3) %inptr, i32 26
diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2.ll b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
index 9b91a3dc9b6e4..c37c7777f617f 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_read2.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
@@ -331,7 +331,7 @@ define amdgpu_kernel void @read2_ptr_is_subreg_arg_f32(ptr addrspace(1) %out, <2
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
- %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
+ %index.0 = insertelement <2 x i32> poison, i32 %x.i, i32 0
%index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0
%gep = getelementptr inbounds float, <2 x ptr addrspace(3)> %lds.ptr, <2 x i32> %index.1
%gep.0 = extractelement <2 x ptr addrspace(3)> %gep, i32 0
@@ -382,7 +382,7 @@ define amdgpu_kernel void @read2_ptr_is_subreg_arg_offset_f32(ptr addrspace(1) %
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
- %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
+ %index.0 = insertelement <2 x i32> poison, i32 %x.i, i32 0
%index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0
%gep = getelementptr inbounds float, <2 x ptr addrspace(3)> %lds.ptr, <2 x i32> %index.1
%gep.0 = extractelement <2 x ptr addrspace(3)> %gep, i32 0
@@ -425,9 +425,9 @@ define amdgpu_kernel void @read2_ptr_is_subreg_f32(ptr addrspace(1) %out) #0 {
; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: s_endpgm
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
- %ptr.0 = insertelement <2 x ptr addrspace(3)> undef, ptr addrspace(3) @lds, i32 0
+ %ptr.0 = insertelement <2 x ptr addrspace(3)> poison, ptr addrspace(3) @lds, i32 0
%ptr.1 = insertelement <2 x ptr addrspace(3)> %ptr.0, ptr addrspace(3) @lds, i32 1
- %x.i.v.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
+ %x.i.v.0 = insertelement <2 x i32> poison, i32 %x.i, i32 0
%x.i.v.1 = insertelement <2 x i32> %x.i.v.0, i32 %x.i, i32 1
%idx = add <2 x i32> %x.i.v.1, <i32 0, i32 8>
%gep = getelementptr inbounds [512 x float], <2 x ptr addrspace(3)> %ptr.1, <2 x i32> <i32 0, i32 0>, <2 x i32> %idx
@@ -1435,7 +1435,7 @@ define amdgpu_ps <2 x float> @ds_read_interp_read(i32 inreg %prims, ptr addrspac
%ptr1 = getelementptr float, ptr addrspace(3) %inptr, i32 4
%v1 = load float, ptr addrspace(3) %ptr1, align 4
%v1b = fadd float %v1, %intrp
- %r0 = insertelement <2 x float> undef, float %v0, i32 0
+ %r0 = insertelement <2 x float> poison, float %v0, i32 0
%r1 = insertelement <2 x float> %r0, float %v1b, i32 1
ret <2 x float> %r1
}
diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll b/llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
index 3aff5ccff4280..bdc31d9161388 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
@@ -161,7 +161,7 @@ define amdgpu_kernel void @simple_read2_v2f32_superreg_scalar_loads_align4(ptr a
%val0 = load float, ptr addrspace(3) %arrayidx0
%val1 = load float, ptr addrspace(3) %arrayidx1
- %vec.0 = insertelement <2 x float> undef, float %val0, i32 0
+ %vec.0 = insertelement <2 x float> poison, float %val0, i32 0
%vec.1 = insertelement <2 x float> %vec.0, float %val1, i32 1
%out.gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %out, i32 %x.i
@@ -188,7 +188,7 @@ define amdgpu_kernel void @simple_read2_v4f32_superreg_scalar_loads_align4(ptr a
%val2 = load float, ptr addrspace(3) %arrayidx2
%val3 = load float, ptr addrspace(3) %arrayidx3
- %vec.0 = insertelement <4 x float> undef, float %val0, i32 0
+ %vec.0 = insertelement <4 x float> poison, float %val0, i32 0
%vec.1 = insertelement <4 x float> %vec.0, float %val1, i32 1
%vec.2 = insertelement <4 x float> %vec.1, float %val2, i32 2
%vec.3 = insertelement <4 x float> %vec.2, float %val3, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/ds_write2.ll b/llvm/test/CodeGen/AMDGPU/ds_write2.ll
index 1f805b6d07f71..e49b181049cc5 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_write2.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_write2.ll
@@ -548,7 +548,7 @@ define amdgpu_kernel void @write2_ptr_subreg_arg_two_val_f32(ptr addrspace(1) %C
%val0 = load float, ptr addrspace(1) %in0.gep, align 4
%val1 = load float, ptr addrspace(1) %in1.gep, align 4
- %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0
+ %index.0 = insertelement <2 x i32> poison, i32 %x.i, i32 0
%index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0
%gep = getelementptr inbounds float, <2 x ptr addrspace(3)> %lds.ptr, <2 x i32> %index.1
%gep.0 = extractelement <2 x ptr addrspace(3)> %gep, i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
index d3b5d45470eb7..bab78aee3ff18 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
@@ -16,7 +16,7 @@ bb:
%tmp = shufflevector <4 x i8> <i8 1, i8 2, i8 3, i8 4>, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
%tmp1 = extractelement <3 x i8> %tmp, i64 0
%tmp2 = zext i8 %tmp1 to i32
- %tmp3 = insertelement <3 x i32> undef, i32 %tmp2, i32 0
+ %tmp3 = insertelement <3 x i32> poison, i32 %tmp2, i32 0
%tmp4 = extractelement <3 x i8> %tmp, i64 1
%tmp5 = zext i8 %tmp4 to i32
%tmp6 = insertelement <3 x i32> %tmp3, i32 %tmp5, i32 1
diff --git a/llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll b/llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
index df31ff0be84ce..cca0dd62aebdd 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
@@ -22,7 +22,7 @@ define amdgpu_kernel void @store_build_vector_multiple_uses_v4i32(ptr addrspace(
%elt2 = load volatile i32, ptr addrspace(1) %in
%elt3 = load volatile i32, ptr addrspace(1) %in
- %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
+ %vec0 = insertelement <4 x i32> poison, i32 %elt0, i32 0
%vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
%vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
%vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3
@@ -64,7 +64,7 @@ define amdgpu_kernel void @store_build_vector_multiple_extract_uses_v4i32(ptr ad
%elt2 = load volatile i32, ptr addrspace(1) %in
%elt3 = load volatile i32, ptr addrspace(1) %in
- %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
+ %vec0 = insertelement <4 x i32> poison, i32 %elt0, i32 0
%vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
%vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
%vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3
@@ -108,7 +108,7 @@ define amdgpu_kernel void @store_build_vector_multiple_uses_v4i32_bitcast_to_v2i
%elt2 = load volatile i32, ptr addrspace(1) %in
%elt3 = load volatile i32, ptr addrspace(1) %in
- %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
+ %vec0 = insertelement <4 x i32> poison, i32 %elt0, i32 0
%vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
%vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
%vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
index e1981972f58d1..32315560f560d 100644
--- a/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
@@ -740,7 +740,7 @@ define <2 x half> @v_test_canonicalize_build_vector_v2f16(<2 x half> %vec) {
%hi = extractelement <2 x half> %vec, i32 1
%lo.op = fadd half %lo, 1.0
%hi.op = fmul half %lo, 4.0
- %ins0 = insertelement <2 x half> undef, half %lo.op, i32 0
+ %ins0 = insertelement <2 x half> poison, half %lo.op, i32 0
%ins1 = insertelement <2 x half> %ins0, half %hi.op, i32 1
%canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %ins1)
ret <2 x half> %canonicalized
diff --git a/llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll b/llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll
index 90fbb6c12382a..54343fa820cba 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll
@@ -32,7 +32,7 @@ define void @global_inst_offset(ptr addrspace(1) nocapture %p) {
define amdgpu_kernel void @load_i16_lo(ptr %arg, ptr %out) {
%gep = getelementptr inbounds i16, ptr %arg, i32 4
%ld = load i16, ptr %gep, align 2
- %vec = insertelement <2 x i16> <i16 undef, i16 0>, i16 %ld, i32 0
+ %vec = insertelement <2 x i16> <i16 poison, i16 0>, i16 %ld, i32 0
%v = add <2 x i16> %vec, %vec
store <2 x i16> %v, ptr %out, align 4
ret void
@@ -44,7 +44,7 @@ define amdgpu_kernel void @load_i16_lo(ptr %arg, ptr %out) {
define amdgpu_kernel void @load_i16_hi(ptr %arg, ptr %out) {
%gep = getelementptr inbounds i16, ptr %arg, i32 4
%ld = load i16, ptr %gep, align 2
- %vec = insertelement <2 x i16> <i16 0, i16 undef>, i16 %ld, i32 1
+ %vec = insertelement <2 x i16> <i16 0, i16 poison>, i16 %ld, i32 1
%v = add <2 x i16> %vec, %vec
store <2 x i16> %v, ptr %out, align 4
ret void
@@ -56,7 +56,7 @@ define amdgpu_kernel void @load_i16_hi(ptr %arg, ptr %out) {
define amdgpu_kernel void @load_half_lo(ptr %arg, ptr %out) {
%gep = getelementptr inbounds half, ptr %arg, i32 4
%ld = load half, ptr %gep, align 2
- %vec = insertelement <2 x half> <half undef, half 0xH0000>, half %ld, i32 0
+ %vec = insertelement <2 x half> <half poison, half 0xH0000>, half %ld, i32 0
%v = fadd <2 x half> %vec, %vec
store <2 x half> %v, ptr %out, align 4
ret void
@@ -68,7 +68,7 @@ define amdgpu_kernel void @load_half_lo(ptr %arg, ptr %out) {
define amdgpu_kernel void @load_half_hi(ptr %arg, ptr %out) {
%gep = getelementptr inbounds half, ptr %arg, i32 4
%ld = load half, ptr %gep, align 2
- %vec = insertelement <2 x half> <half 0xH0000, half undef>, half %ld, i32 1
+ %vec = insertelement <2 x half> <half 0xH0000, half poison>, half %ld, i32 1
%v = fadd <2 x half> %vec, %vec
store <2 x half> %v, ptr %out, align 4
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/floor.ll b/llvm/test/CodeGen/AMDGPU/floor.ll
index cc23289b20b0a..adfcd98ba3681 100644
--- a/llvm/test/CodeGen/AMDGPU/floor.ll
+++ b/llvm/test/CodeGen/AMDGPU/floor.ll
@@ -4,7 +4,7 @@
define amdgpu_ps void @test(<4 x float> inreg %reg0) {
%r0 = extractelement <4 x float> %reg0, i32 0
%r1 = call float @floorf(float %r0)
- %vec = insertelement <4 x float> undef, float %r1, i32 0
+ %vec = insertelement <4 x float> poison, float %r1, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/fmac.sdwa.ll b/llvm/test/CodeGen/AMDGPU/fmac.sdwa.ll
index 4f49d4ce3a040..dc60007cad977 100644
--- a/llvm/test/CodeGen/AMDGPU/fmac.sdwa.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmac.sdwa.ll
@@ -38,7 +38,7 @@ bb14: ; preds = %bb14, %bb11
%tmp24 = getelementptr inbounds float, ptr addrspace(4) %arg1, i64 %tmp23
%tmp25 = load float, ptr addrspace(4) %tmp24, align 4
%tmp26 = fptrunc float %tmp25 to half
- %tmp27 = insertelement <4 x half> undef, half %tmp26, i32 0
+ %tmp27 = insertelement <4 x half> poison, half %tmp26, i32 0
%tmp28 = shufflevector <4 x half> %tmp27, <4 x half> undef, <4 x i32> zeroinitializer
%vec.A.0 = extractelement <4 x half> %tmp21, i32 0
%vec.B.0 = extractelement <4 x half> %tmp28, i32 0
@@ -56,7 +56,7 @@ bb14: ; preds = %bb14, %bb11
%vec.B.3 = extractelement <4 x half> %tmp28, i32 3
%vec.C.3 = extractelement <4 x half> %tmp15, i32 3
%vec.res.3 = tail call half @llvm.fmuladd.f16(half %vec.A.3, half %vec.B.3, half %vec.C.3)
- %full.res.0 = insertelement <4 x half> undef, half %vec.res.0, i32 0
+ %full.res.0 = insertelement <4 x half> poison, half %vec.res.0, i32 0
%full.res.1 = insertelement <4 x half> %full.res.0, half %vec.res.1, i32 1
%full.res.2 = insertelement <4 x half> %full.res.1, half %vec.res.2, i32 2
%tmp29 = insertelement <4 x half> %full.res.2, half %vec.res.3, i32 3
@@ -80,7 +80,7 @@ define linkonce_odr hidden <4 x half> @_Z13convert_half4Dv4_h(<4 x i8> %arg) loc
bb:
%tmp = extractelement <4 x i8> %arg, i64 0
%tmp1 = uitofp i8 %tmp to half
- %tmp2 = insertelement <4 x half> undef, half %tmp1, i32 0
+ %tmp2 = insertelement <4 x half> poison, half %tmp1, i32 0
%tmp3 = extractelement <4 x i8> %arg, i64 1
%tmp4 = uitofp i8 %tmp3 to half
%tmp5 = insertelement <4 x half> %tmp2, half %tmp4, i32 1
diff --git a/llvm/test/CodeGen/AMDGPU/fmad-formation-fmul-distribute-denormal-mode.ll b/llvm/test/CodeGen/AMDGPU/fmad-formation-fmul-distribute-denormal-mode.ll
index 25776bb8380ae..92eb4a642dc92 100644
--- a/llvm/test/CodeGen/AMDGPU/fmad-formation-fmul-distribute-denormal-mode.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmad-formation-fmul-distribute-denormal-mode.ll
@@ -236,7 +236,7 @@ define <2 x float> @unsafe_fast_fmul_fadd_distribute_post_legalize_f32(float %ar
; FMADGFX10-NEXT: v_mad_f32 v0, v0, v1, v1
; FMADGFX10-NEXT: s_setpc_b64 s[30:31]
%add = fadd fast float %arg0, 1.0
- %splat = insertelement <2 x float> undef, float %add, i32 0
+ %splat = insertelement <2 x float> poison, float %add, i32 0
%tmp1 = fmul fast <2 x float> %arg1, %splat
ret <2 x float> %tmp1
}
@@ -279,7 +279,7 @@ define <2 x float> @unsafe_fast_fmul_fsub_ditribute_post_legalize(float %arg0, <
; FMADGFX10-NEXT: v_mad_f32 v0, -v0, v1, v1
; FMADGFX10-NEXT: s_setpc_b64 s[30:31]
%sub = fsub fast float 1.0, %arg0
- %splat = insertelement <2 x float> undef, float %sub, i32 0
+ %splat = insertelement <2 x float> poison, float %sub, i32 0
%tmp1 = fmul fast <2 x float> %arg1, %splat
ret <2 x float> %tmp1
}
diff --git a/llvm/test/CodeGen/AMDGPU/fmad.ll b/llvm/test/CodeGen/AMDGPU/fmad.ll
index a1d62228fd4b6..f21ad11b1b06f 100644
--- a/llvm/test/CodeGen/AMDGPU/fmad.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmad.ll
@@ -8,7 +8,7 @@ define amdgpu_ps void @test(<4 x float> inreg %reg0) {
%r2 = extractelement <4 x float> %reg0, i32 2
%r3 = fmul float %r0, %r1
%r4 = fadd float %r3, %r2
- %vec = insertelement <4 x float> undef, float %r4, i32 0
+ %vec = insertelement <4 x float> poison, float %r4, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/fmax.ll b/llvm/test/CodeGen/AMDGPU/fmax.ll
index 825ad93b896c5..d94b4cbf28e06 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax.ll
@@ -7,7 +7,7 @@ define amdgpu_ps void @test(<4 x float> inreg %reg0) {
%r1 = extractelement <4 x float> %reg0, i32 1
%r2 = fcmp oge float %r0, %r1
%r3 = select i1 %r2, float %r0, float %r1
- %vec = insertelement <4 x float> undef, float %r3, i32 0
+ %vec = insertelement <4 x float> poison, float %r3, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/fmin.ll b/llvm/test/CodeGen/AMDGPU/fmin.ll
index e7cb2d7532483..530636af96038 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin.ll
@@ -7,7 +7,7 @@ define amdgpu_ps void @test(<4 x float> inreg %reg0) {
%r1 = extractelement <4 x float> %reg0, i32 1
%r2 = fcmp uge float %r0, %r1
%r3 = select i1 %r2, float %r1, float %r0
- %vec = insertelement <4 x float> undef, float %r3, i32 0
+ %vec = insertelement <4 x float> poison, float %r3, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
index f4c5ebd8b3cf5..78afde138944e 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
@@ -1466,7 +1466,7 @@ define <2 x half> @v_fneg_minnum_multi_use_minnum_f16_no_ieee(half %a, half %b)
%min = call half @llvm.minnum.f16(half %a, half %b)
%fneg = fneg half %min
%use1 = fmul half %min, 4.0
- %ins0 = insertelement <2 x half> undef, half %fneg, i32 0
+ %ins0 = insertelement <2 x half> poison, half %fneg, i32 0
%ins1 = insertelement <2 x half> %ins0, half %use1, i32 1
ret <2 x half> %ins1
}
@@ -1904,7 +1904,7 @@ define <2 x half> @v_fneg_maxnum_multi_use_maxnum_f16_no_ieee(half %a, half %b)
%max = call half @llvm.maxnum.f16(half %a, half %b)
%fneg = fneg half %max
%use1 = fmul half %max, 4.0
- %ins0 = insertelement <2 x half> undef, half %fneg, i32 0
+ %ins0 = insertelement <2 x half> poison, half %fneg, i32 0
%ins1 = insertelement <2 x half> %ins0, half %use1, i32 1
ret <2 x half> %ins1
}
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.ll
index 0cb4b8c960bbf..3a178b73ebd6c 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.ll
@@ -853,7 +853,7 @@ define amdgpu_ps <2 x float> @v_fneg_minnum_multi_use_minnum_f32_no_ieee(float %
%min = call float @llvm.minnum.f32(float %a, float %b)
%fneg = fneg float %min
%use1 = fmul float %min, 4.0
- %ins0 = insertelement <2 x float> undef, float %fneg, i32 0
+ %ins0 = insertelement <2 x float> poison, float %fneg, i32 0
%ins1 = insertelement <2 x float> %ins0, float %use1, i32 1
ret <2 x float> %ins1
}
@@ -1093,7 +1093,7 @@ define amdgpu_ps <2 x float> @v_fneg_maxnum_multi_use_maxnum_f32_no_ieee(float %
%max = call float @llvm.maxnum.f32(float %a, float %b)
%fneg = fneg float %max
%use1 = fmul float %max, 4.0
- %ins0 = insertelement <2 x float> undef, float %fneg, i32 0
+ %ins0 = insertelement <2 x float> poison, float %fneg, i32 0
%ins1 = insertelement <2 x float> %ins0, float %use1, i32 1
ret <2 x float> %ins1
}
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
index 9a72fe96b5c3a..14f7cbcd0f438 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
@@ -1186,7 +1186,7 @@ define <2 x float> @v_fneg_minnum_multi_use_minnum_f32_no_ieee(float %a, float %
%min = call float @llvm.minnum.f32(float %a, float %b)
%fneg = fneg float %min
%use1 = fmul float %min, 4.0
- %ins0 = insertelement <2 x float> undef, float %fneg, i32 0
+ %ins0 = insertelement <2 x float> poison, float %fneg, i32 0
%ins1 = insertelement <2 x float> %ins0, float %use1, i32 1
ret <2 x float> %ins1
}
@@ -1376,7 +1376,7 @@ define <2 x float> @v_fneg_maxnum_multi_use_maxnum_f32_no_ieee(float %a, float %
%max = call float @llvm.maxnum.f32(float %a, float %b)
%fneg = fneg float %max
%use1 = fmul float %max, 4.0
- %ins0 = insertelement <2 x float> undef, float %fneg, i32 0
+ %ins0 = insertelement <2 x float> poison, float %fneg, i32 0
%ins1 = insertelement <2 x float> %ins0, float %use1, i32 1
ret <2 x float> %ins1
}
diff --git a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
index 7125e7740c10a..aa5f72a15c2f3 100644
--- a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
+++ b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
@@ -254,7 +254,7 @@ declare void @func(ptr addrspace(5) nocapture) #0
define void @undefined_stack_store_reg(float %arg, i32 %arg1) #0 {
bb:
%tmp = alloca <4 x float>, align 16, addrspace(5)
- %tmp2 = insertelement <4 x float> undef, float %arg, i32 0
+ %tmp2 = insertelement <4 x float> poison, float %arg, i32 0
store <4 x float> %tmp2, ptr addrspace(5) undef
%tmp3 = icmp eq i32 %arg1, 0
br i1 %tmp3, label %bb4, label %bb5
diff --git a/llvm/test/CodeGen/AMDGPU/function-returns.ll b/llvm/test/CodeGen/AMDGPU/function-returns.ll
index 6e60c812f7c0c..128f40a34de89 100644
--- a/llvm/test/CodeGen/AMDGPU/function-returns.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-returns.ll
@@ -2207,7 +2207,7 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
%load2 = load volatile i32, ptr addrspace(3) undef
%load3 = load volatile i32, ptr addrspace(3) undef
- %insert.0 = insertelement <3 x i32> undef, i32 %load0, i32 0
+ %insert.0 = insertelement <3 x i32> poison, i32 %load0, i32 0
%insert.1 = insertelement <3 x i32> %insert.0, i32 %load1, i32 1
%insert.2 = insertelement <3 x i32> %insert.1, i32 %load2, i32 2
%insert.3 = insertvalue { <3 x i32>, i32 } poison, <3 x i32> %insert.2, 0
@@ -2266,7 +2266,7 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
%load2 = load volatile float, ptr addrspace(3) undef
%load3 = load volatile i32, ptr addrspace(3) undef
- %insert.0 = insertelement <3 x float> undef, float %load0, i32 0
+ %insert.0 = insertelement <3 x float> poison, float %load0, i32 0
%insert.1 = insertelement <3 x float> %insert.0, float %load1, i32 1
%insert.2 = insertelement <3 x float> %insert.1, float %load2, i32 2
%insert.3 = insertvalue { <3 x float>, i32 } poison, <3 x float> %insert.2, 0
diff --git a/llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll b/llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
index b9592a9ff9073..e2d33df64dec2 100644
--- a/llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
@@ -85,7 +85,7 @@ bb3: ; preds = %bb3, %bb
%i4 = zext i32 %i to i64
%i5 = getelementptr inbounds i16, ptr addrspace(1) %arg, i64 %i4
%i6 = load volatile i16, ptr addrspace(1) %i5, align 4
- %insertelt = insertelement <2 x i16> undef, i16 %i6, i32 1
+ %insertelt = insertelement <2 x i16> poison, i16 %i6, i32 1
%i8 = bitcast <2 x i16> %insertelt to i32
%i9 = icmp eq i32 %i8, 256
br i1 %i9, label %bb2, label %bb3
diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
index bc49f70cbee11..0cd75f3fc208c 100644
--- a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
@@ -3849,7 +3849,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_undef_hi(ptr addrspace(
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
%load = load i16, ptr addrspace(1) %gep0
- %build = insertelement <2 x i16> undef, i16 %load, i32 0
+ %build = insertelement <2 x i16> poison, i16 %load, i32 0
%cast = bitcast <2 x i16> %build to <2 x half>
ret <2 x half> %cast
}
@@ -3882,7 +3882,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_undef_hi_immneg128(ptr
%gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128
%load = load i16, ptr addrspace(1) %gep1
- %build = insertelement <2 x i16> undef, i16 %load, i32 0
+ %build = insertelement <2 x i16> poison, i16 %load, i32 0
%cast = bitcast <2 x i16> %build to <2 x half>
ret <2 x half> %cast
}
@@ -4225,7 +4225,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_undef_hi(ptr addrspace(
%zext.offset = zext i32 %voffset to i64
%gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
%load = load i16, ptr addrspace(1) %gep0
- %build = insertelement <2 x i16> undef, i16 %load, i32 1
+ %build = insertelement <2 x i16> poison, i16 %load, i32 1
%cast = bitcast <2 x i16> %build to <2 x half>
ret <2 x half> %cast
}
@@ -4259,7 +4259,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_undef_hi_immneg128(ptr
%gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset
%gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 -128
%load = load i16, ptr addrspace(1) %gep1
- %build = insertelement <2 x i16> undef, i16 %load, i32 1
+ %build = insertelement <2 x i16> poison, i16 %load, i32 1
%cast = bitcast <2 x i16> %build to <2 x half>
ret <2 x half> %cast
}
diff --git a/llvm/test/CodeGen/AMDGPU/image-schedule.ll b/llvm/test/CodeGen/AMDGPU/image-schedule.ll
index dbd9efc58e59d..09e819de074ff 100644
--- a/llvm/test/CodeGen/AMDGPU/image-schedule.ll
+++ b/llvm/test/CodeGen/AMDGPU/image-schedule.ll
@@ -14,7 +14,7 @@ define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg %arg, i32 inreg %arg1
.entry:
%tmp = call i64 @llvm.amdgcn.s.getpc() #1
%tmp6 = bitcast i64 %tmp to <2 x i32>
- %.0.vec.insert = insertelement <2 x i32> undef, i32 %arg2, i32 0
+ %.0.vec.insert = insertelement <2 x i32> poison, i32 %arg2, i32 0
%.4.vec.insert = shufflevector <2 x i32> %.0.vec.insert, <2 x i32> %tmp6, <2 x i32> <i32 0, i32 3>
%tmp7 = bitcast <2 x i32> %.4.vec.insert to i64
%tmp8 = inttoptr i64 %tmp7 to ptr addrspace(4)
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
index 56a3ce7281030..a7e31375f425e 100644
--- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
+++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
@@ -1880,7 +1880,7 @@ define amdgpu_kernel void @insert_undef_offset_sgpr_vector_src(ptr addrspace(1)
; GFX9-IDXMODE-NEXT: s_endpgm
entry:
%ld = load <4 x i32>, ptr addrspace(1) %in
- %value = insertelement <4 x i32> %ld, i32 5, i32 undef
+ %value = insertelement <4 x i32> %ld, i32 5, i32 poison
store <4 x i32> %value, ptr addrspace(1) %out
ret void
}
@@ -7699,13 +7699,13 @@ bb:
bb1:
%tmp2 = load volatile <4 x float>, ptr addrspace(1) undef
- %tmp3 = insertelement <4 x float> %tmp2, float %val0, i32 undef
+ %tmp3 = insertelement <4 x float> %tmp2, float %val0, i32 poison
call void asm sideeffect "; reg use $0", "v"(<4 x float> %tmp3) ; Prevent block optimize out
br label %bb7
bb4:
%tmp5 = load volatile <4 x float>, ptr addrspace(1) undef
- %tmp6 = insertelement <4 x float> %tmp5, float %val0, i32 undef
+ %tmp6 = insertelement <4 x float> %tmp5, float %val0, i32 poison
call void asm sideeffect "; reg use $0", "v"(<4 x float> %tmp6) ; Prevent block optimize out
br label %bb7
@@ -9459,7 +9459,7 @@ bb2:
bb4:
%vgpr = load volatile i32, ptr addrspace(1) undef
- %tmp5 = insertelement <16 x i32> undef, i32 undef, i32 %vgpr
+ %tmp5 = insertelement <16 x i32> poison, i32 poison, i32 %vgpr
%tmp6 = insertelement <16 x i32> %tmp5, i32 %arg1, i32 %vgpr
%tmp7 = extractelement <16 x i32> %tmp6, i32 0
br label %bb2
diff --git a/llvm/test/CodeGen/AMDGPU/input-mods.r600.ll b/llvm/test/CodeGen/AMDGPU/input-mods.r600.ll
index 4db5e2a472ee7..633ad6acebd4f 100644
--- a/llvm/test/CodeGen/AMDGPU/input-mods.r600.ll
+++ b/llvm/test/CodeGen/AMDGPU/input-mods.r600.ll
@@ -43,7 +43,7 @@ define amdgpu_ps void @test(<4 x float> inreg %reg0) {
%r1 = call float @llvm.fabs.f32(float %r0)
%r2 = fsub float -0.000000e+00, %r1
%r3 = call afn float @llvm.exp2.f32(float %r2)
- %vec = insertelement <4 x float> undef, float %r3, i32 0
+ %vec = insertelement <4 x float> poison, float %r3, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
index add8c0f75bf33..6f0c850117208 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
@@ -48,7 +48,7 @@ define amdgpu_kernel void @float4_inselt_undef(ptr addrspace(1) %out, i32 %sel)
; GCN-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NEXT: s_endpgm
entry:
- %v = insertelement <4 x float> undef, float 1.000000e+00, i32 %sel
+ %v = insertelement <4 x float> poison, float 1.000000e+00, i32 %sel
store <4 x float> %v, ptr addrspace(1) %out
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
index f213b0635c8ac..8720fda9646e2 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
@@ -2016,7 +2016,7 @@ define amdgpu_kernel void @insert_split_bb(ptr addrspace(1) %out, ptr addrspace(
; VI-NEXT: .LBB42_4:
; VI-NEXT: s_branch .LBB42_2
entry:
- %0 = insertelement <2 x i32> undef, i32 %a, i32 0
+ %0 = insertelement <2 x i32> poison, i32 %a, i32 0
%1 = icmp eq i32 %a, 0
br i1 %1, label %if, label %else
diff --git a/llvm/test/CodeGen/AMDGPU/jump-address.ll b/llvm/test/CodeGen/AMDGPU/jump-address.ll
index 0747133c0c581..d58db378e1384 100644
--- a/llvm/test/CodeGen/AMDGPU/jump-address.ll
+++ b/llvm/test/CodeGen/AMDGPU/jump-address.ll
@@ -32,7 +32,7 @@ ENDIF: ; preds = %IF13, %ELSE, %main_
%temp1.0 = phi float [ 0.000000e+00, %main_body ], [ %23, %IF13 ], [ 0.000000e+00, %ELSE ]
%temp2.0 = phi float [ 1.000000e+00, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
%temp3.0 = phi float [ 5.000000e-01, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
- %16 = insertelement <4 x float> undef, float %temp.0, i32 0
+ %16 = insertelement <4 x float> poison, float %temp.0, i32 0
%17 = insertelement <4 x float> %16, float %temp1.0, i32 1
%18 = insertelement <4 x float> %17, float %temp2.0, i32 2
%19 = insertelement <4 x float> %18, float %temp3.0, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/kcache-fold.ll b/llvm/test/CodeGen/AMDGPU/kcache-fold.ll
index c3b41af529ecd..f00b8db963337 100644
--- a/llvm/test/CodeGen/AMDGPU/kcache-fold.ll
+++ b/llvm/test/CodeGen/AMDGPU/kcache-fold.ll
@@ -44,7 +44,7 @@ main_body:
%clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
%max.0.i1 = call float @llvm.maxnum.f32(float %tmp37, float 0.000000e+00)
%clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
- %tmp38 = insertelement <4 x float> undef, float %clamp.i, i32 0
+ %tmp38 = insertelement <4 x float> poison, float %clamp.i, i32 0
%tmp39 = insertelement <4 x float> %tmp38, float %clamp.i6, i32 1
%tmp40 = insertelement <4 x float> %tmp39, float %clamp.i4, i32 2
%tmp41 = insertelement <4 x float> %tmp40, float %clamp.i2, i32 3
@@ -96,7 +96,7 @@ main_body:
%clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
%max.0.i1 = call float @llvm.maxnum.f32(float %tmp37, float 0.000000e+00)
%clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
- %tmp38 = insertelement <4 x float> undef, float %clamp.i, i32 0
+ %tmp38 = insertelement <4 x float> poison, float %clamp.i, i32 0
%tmp39 = insertelement <4 x float> %tmp38, float %clamp.i6, i32 1
%tmp40 = insertelement <4 x float> %tmp39, float %clamp.i4, i32 2
%tmp41 = insertelement <4 x float> %tmp40, float %clamp.i2, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/lds-bounds.ll b/llvm/test/CodeGen/AMDGPU/lds-bounds.ll
index 942b4f7cf4cbc..c7307cc6f552a 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-bounds.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-bounds.ll
@@ -24,7 +24,7 @@ entry:
%v.0 = load i32, ptr addrspace(3) %ptr, align 8
%v.1 = load i32, ptr addrspace(3) %ptr.gep.1
- %r.0 = insertelement <2 x i32> undef, i32 %v.0, i32 0
+ %r.0 = insertelement <2 x i32> poison, i32 %v.0, i32 0
%r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1
%bc = bitcast <2 x i32> %r.1 to <2 x float>
ret <2 x float> %bc
@@ -54,7 +54,7 @@ entry:
%v.0 = load i32, ptr addrspace(3) %ptr.a
%v.1 = load i32, ptr addrspace(3) %ptr.b
- %r.0 = insertelement <2 x i32> undef, i32 %v.0, i32 0
+ %r.0 = insertelement <2 x i32> poison, i32 %v.0, i32 0
%r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1
%bc = bitcast <2 x i32> %r.1 to <2 x float>
ret <2 x float> %bc
@@ -88,7 +88,7 @@ entry:
%v.0 = load i32, ptr addrspace(3) %ptr.a
%v.1 = load i32, ptr addrspace(3) %ptr.b
- %r.0 = insertelement <2 x i32> undef, i32 %v.0, i32 0
+ %r.0 = insertelement <2 x i32> poison, i32 %v.0, i32 0
%r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1
%bc = bitcast <2 x i32> %r.1 to <2 x float>
ret <2 x float> %bc
@@ -120,7 +120,7 @@ entry:
%v.0 = load i32, ptr addrspace(3) %ptr.a
%v.1 = load i32, ptr addrspace(3) %ptr.b
- %r.0 = insertelement <2 x i32> undef, i32 %v.0, i32 0
+ %r.0 = insertelement <2 x i32> poison, i32 %v.0, i32 0
%r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1
%bc = bitcast <2 x i32> %r.1 to <2 x float>
ret <2 x float> %bc
diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll b/llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
index 5cb3ca0b80b66..3cf02be69d3fe 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
@@ -32,7 +32,7 @@ main_body:
%val.0 = load float, ptr addrspace(3) %gep.0, align 4
call void @llvm.amdgcn.wave.barrier()
%val.1 = load float, ptr addrspace(3) %gep.1, align 4
- %tmp.0 = insertelement <2 x float> undef, float %val.0, i32 0
+ %tmp.0 = insertelement <2 x float> poison, float %val.0, i32 0
%res = insertelement <2 x float> %tmp.0, float %val.1, i32 1
store <2 x float> %res, ptr addrspace(1) %out
ret void
@@ -60,7 +60,7 @@ main_body:
%val.0 = load float, ptr addrspace(3) %gep.0, align 4
call void @llvm.amdgcn.wave.barrier()
%val.1 = load float, ptr addrspace(3) %gep.1, align 4
- %tmp.0 = insertelement <2 x float> undef, float %val.0, i32 0
+ %tmp.0 = insertelement <2 x float> poison, float %val.0, i32 0
%res = insertelement <2 x float> %tmp.0, float %val.1, i32 1
store <2 x float> %res, ptr addrspace(1) %out
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll b/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
index 01af334652382..278ad63b0b76c 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
@@ -18,7 +18,7 @@ bb:
%load = load <2 x i32>, ptr addrspace(3) %gep, align 4
%v1 = extractelement <2 x i32> %load, i32 0
%v2 = extractelement <2 x i32> %load, i32 1
- %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
+ %v3 = insertelement <2 x i32> poison, i32 %v2, i32 0
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
store <2 x i32> %v4, ptr addrspace(3) %gep, align 4
ret void
@@ -38,7 +38,7 @@ bb:
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
- %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
+ %v5 = insertelement <4 x i32> poison, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
@@ -59,7 +59,7 @@ bb:
%v1 = extractelement <3 x i32> %load, i32 0
%v2 = extractelement <3 x i32> %load, i32 1
%v3 = extractelement <3 x i32> %load, i32 2
- %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
+ %v5 = insertelement <3 x i32> poison, i32 %v3, i32 0
%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
store <3 x i32> %v7, ptr addrspace(3) %gep, align 4
@@ -80,7 +80,7 @@ bb:
%load = load <2 x i32>, ptr %gep, align 4
%v1 = extractelement <2 x i32> %load, i32 0
%v2 = extractelement <2 x i32> %load, i32 1
- %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
+ %v3 = insertelement <2 x i32> poison, i32 %v2, i32 0
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
store <2 x i32> %v4, ptr %gep, align 4
ret void
@@ -106,7 +106,7 @@ bb:
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
- %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
+ %v5 = insertelement <4 x i32> poison, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
@@ -131,7 +131,7 @@ bb:
%v1 = extractelement <3 x i32> %load, i32 0
%v2 = extractelement <3 x i32> %load, i32 1
%v3 = extractelement <3 x i32> %load, i32 2
- %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
+ %v5 = insertelement <3 x i32> poison, i32 %v3, i32 0
%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
store <3 x i32> %v7, ptr %gep, align 4
@@ -148,7 +148,7 @@ bb:
%load = load <2 x i32>, ptr addrspace(3) %gep, align 8
%v1 = extractelement <2 x i32> %load, i32 0
%v2 = extractelement <2 x i32> %load, i32 1
- %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
+ %v3 = insertelement <2 x i32> poison, i32 %v2, i32 0
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
store <2 x i32> %v4, ptr addrspace(3) %gep, align 8
ret void
@@ -165,7 +165,7 @@ bb:
%v1 = extractelement <3 x i32> %load, i32 0
%v2 = extractelement <3 x i32> %load, i32 1
%v3 = extractelement <3 x i32> %load, i32 2
- %v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
+ %v5 = insertelement <3 x i32> poison, i32 %v3, i32 0
%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
store <3 x i32> %v7, ptr addrspace(3) %gep, align 16
@@ -182,7 +182,7 @@ bb:
%load = load <2 x i32>, ptr %gep, align 8
%v1 = extractelement <2 x i32> %load, i32 0
%v2 = extractelement <2 x i32> %load, i32 1
- %v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
+ %v3 = insertelement <2 x i32> poison, i32 %v2, i32 0
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
store <2 x i32> %v4, ptr %gep, align 8
ret void
@@ -200,7 +200,7 @@ bb:
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
- %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
+ %v5 = insertelement <4 x i32> poison, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
@@ -222,7 +222,7 @@ bb:
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
- %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
+ %v5 = insertelement <4 x i32> poison, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
@@ -246,7 +246,7 @@ bb:
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
- %v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
+ %v5 = insertelement <4 x i32> poison, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
index 22b4c5a7362ad..2d1a055066fdf 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
@@ -54,7 +54,7 @@ define amdgpu_ps <2 x float> @sample_contig_nsa(<8 x i32> inreg %rsrc, <4 x i32>
main_body:
%v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
- %r.0 = insertelement <2 x float> undef, float %v1, i32 0
+ %r.0 = insertelement <2 x float> poison, float %v1, i32 0
%r = insertelement <2 x float> %r.0, float %v2, i32 1
ret <2 x float> %r
}
@@ -70,7 +70,7 @@ define amdgpu_ps <2 x float> @sample_nsa_nsa(<8 x i32> inreg %rsrc, <4 x i32> in
main_body:
%v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
- %r.0 = insertelement <2 x float> undef, float %v1, i32 0
+ %r.0 = insertelement <2 x float> poison, float %v1, i32 0
%r = insertelement <2 x float> %r.0, float %v2, i32 1
ret <2 x float> %r
}
@@ -86,7 +86,7 @@ define amdgpu_ps <2 x float> @sample_nsa_contig(<8 x i32> inreg %rsrc, <4 x i32>
main_body:
%v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
- %r.0 = insertelement <2 x float> undef, float %v1, i32 0
+ %r.0 = insertelement <2 x float> poison, float %v1, i32 0
%r = insertelement <2 x float> %r.0, float %v2, i32 1
ret <2 x float> %r
}
@@ -106,7 +106,7 @@ define amdgpu_ps <2 x float> @sample_contig_contig(<8 x i32> inreg %rsrc, <4 x i
main_body:
%v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare, float %s1, float %t1, float %r1, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2, float %t2, float %r2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
- %r.0 = insertelement <2 x float> undef, float %v1, i32 0
+ %r.0 = insertelement <2 x float> poison, float %v1, i32 0
%r = insertelement <2 x float> %r.0, float %v2, i32 1
ret <2 x float> %r
}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
index be66d6516f438..389acd31a9d08 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
@@ -259,7 +259,7 @@ main_body:
%tex.vec = extractvalue {<2 x half>, i32} %tex, 0
%tex.err = extractvalue {<2 x half>, i32} %tex, 1
%tex.vecf = bitcast <2 x half> %tex.vec to float
- %r.0 = insertelement <2 x float> undef, float %tex.vecf, i32 0
+ %r.0 = insertelement <2 x float> poison, float %tex.vecf, i32 0
%tex.errf = bitcast i32 %tex.err to float
%r = insertelement <2 x float> %r.0, float %tex.errf, i32 1
ret <2 x float> %r
@@ -415,7 +415,7 @@ main_body:
%tex.vecf = bitcast <4 x half> %tex.vec_wide to <2 x float>
%tex.vecf.0 = extractelement <2 x float> %tex.vecf, i32 0
%tex.vecf.1 = extractelement <2 x float> %tex.vecf, i32 1
- %r.0 = insertelement <4 x float> undef, float %tex.vecf.0, i32 0
+ %r.0 = insertelement <4 x float> poison, float %tex.vecf.0, i32 0
%r.1 = insertelement <4 x float> %r.0, float %tex.vecf.1, i32 1
%tex.errf = bitcast i32 %tex.err to float
%r = insertelement <4 x float> %r.1, float %tex.errf, i32 2
@@ -571,7 +571,7 @@ main_body:
%tex.vecf = bitcast <4 x half> %tex.vec to <2 x float>
%tex.vecf.0 = extractelement <2 x float> %tex.vecf, i32 0
%tex.vecf.1 = extractelement <2 x float> %tex.vecf, i32 1
- %r.0 = insertelement <4 x float> undef, float %tex.vecf.0, i32 0
+ %r.0 = insertelement <4 x float> poison, float %tex.vecf.0, i32 0
%r.1 = insertelement <4 x float> %r.0, float %tex.vecf.1, i32 1
%tex.errf = bitcast i32 %tex.err to float
%r = insertelement <4 x float> %r.1, float %tex.errf, i32 2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
index c8421c66f97c3..6d8ce071371c9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
@@ -207,7 +207,7 @@ main_body:
%res.f = extractelement <4 x float> %res.vec, i32 0
%res.err = extractvalue {<4 x float>,i32} %v, 1
%res.errf = bitcast i32 %res.err to float
- %res.tmp = insertelement <2 x float> undef, float %res.f, i32 0
+ %res.tmp = insertelement <2 x float> poison, float %res.f, i32 0
%res = insertelement <2 x float> %res.tmp, float %res.errf, i32 1
ret <2 x float> %res
}
@@ -266,7 +266,7 @@ main_body:
%res.f = extractelement <4 x float> %res.vec, i32 1
%res.err = extractvalue {<4 x float>,i32} %v, 1
%res.errf = bitcast i32 %res.err to float
- %res.tmp = insertelement <2 x float> undef, float %res.f, i32 0
+ %res.tmp = insertelement <2 x float> poison, float %res.f, i32 0
%res = insertelement <2 x float> %res.tmp, float %res.errf, i32 1
ret <2 x float> %res
}
@@ -325,7 +325,7 @@ main_body:
%res.f = extractelement <4 x float> %res.vec, i32 2
%res.err = extractvalue {<4 x float>,i32} %v, 1
%res.errf = bitcast i32 %res.err to float
- %res.tmp = insertelement <2 x float> undef, float %res.f, i32 0
+ %res.tmp = insertelement <2 x float> poison, float %res.f, i32 0
%res = insertelement <2 x float> %res.tmp, float %res.errf, i32 1
ret <2 x float> %res
}
@@ -384,7 +384,7 @@ main_body:
%res.f = extractelement <4 x float> %res.vec, i32 3
%res.err = extractvalue {<4 x float>,i32} %v, 1
%res.errf = bitcast i32 %res.err to float
- %res.tmp = insertelement <2 x float> undef, float %res.f, i32 0
+ %res.tmp = insertelement <2 x float> poison, float %res.f, i32 0
%res = insertelement <2 x float> %res.tmp, float %res.errf, i32 1
ret <2 x float> %res
}
@@ -458,7 +458,7 @@ main_body:
%res.f2 = extractelement <4 x float> %res.vec, i32 1
%res.err = extractvalue {<4 x float>,i32} %v, 1
%res.errf = bitcast i32 %res.err to float
- %res.tmp1 = insertelement <4 x float> undef, float %res.f1, i32 0
+ %res.tmp1 = insertelement <4 x float> poison, float %res.f1, i32 0
%res.tmp2 = insertelement <4 x float> %res.tmp1, float %res.f2, i32 1
%res = insertelement <4 x float> %res.tmp2, float %res.errf, i32 2
ret <4 x float> %res
@@ -533,7 +533,7 @@ main_body:
%res.f2 = extractelement <4 x float> %res.vec, i32 3
%res.err = extractvalue {<4 x float>,i32} %v, 1
%res.errf = bitcast i32 %res.err to float
- %res.tmp1 = insertelement <4 x float> undef, float %res.f1, i32 0
+ %res.tmp1 = insertelement <4 x float> poison, float %res.f1, i32 0
%res.tmp2 = insertelement <4 x float> %res.tmp1, float %res.f2, i32 1
%res = insertelement <4 x float> %res.tmp2, float %res.errf, i32 2
ret <4 x float> %res
@@ -602,7 +602,7 @@ main_body:
%res.f3 = extractelement <4 x float> %res.vec, i32 3
%res.err = extractvalue {<4 x float>,i32} %v, 1
%res.errf = bitcast i32 %res.err to float
- %res.tmp1 = insertelement <4 x float> undef, float %res.f1, i32 0
+ %res.tmp1 = insertelement <4 x float> poison, float %res.f1, i32 0
%res.tmp2 = insertelement <4 x float> %res.tmp1, float %res.f2, i32 1
%res.tmp3 = insertelement <4 x float> %res.tmp2, float %res.f3, i32 2
%res = insertelement <4 x float> %res.tmp3, float %res.errf, i32 3
@@ -2144,7 +2144,7 @@ main_body:
%v.f2 = extractelement <2 x float> %v.vec, i32 1
%v.err = extractvalue {<2 x float>, i32} %v, 1
%v.errf = bitcast i32 %v.err to float
- %res.0 = insertelement <4 x float> undef, float %v.f1, i32 0
+ %res.0 = insertelement <4 x float> poison, float %v.f1, i32 0
%res.1 = insertelement <4 x float> %res.0, float %v.f2, i32 1
%res.2 = insertelement <4 x float> %res.1, float %v.errf, i32 2
ret <4 x float> %res.2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
index 8af5db9f62908..33a0ed2caa9e6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
@@ -33,13 +33,13 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray(i32 %node_ptr, float %ray_
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: ; return to shader part epilog
main_body:
- %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
+ %ray_origin0 = insertelement <3 x float> poison, float %ray_origin_x, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
- %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
+ %ray_dir0 = insertelement <3 x float> poison, float %ray_dir_x, i32 0
%ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
%ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
- %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
+ %ray_inv_dir0 = insertelement <3 x float> poison, float %ray_inv_dir_x, i32 0
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
@@ -152,13 +152,13 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray(<2 x i32> %node_ptr_vec,
; GFX12-NEXT: ; return to shader part epilog
main_body:
%node_ptr = bitcast <2 x i32> %node_ptr_vec to i64
- %ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
+ %ray_origin0 = insertelement <3 x float> poison, float %ray_origin_x, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
- %ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
+ %ray_dir0 = insertelement <3 x float> poison, float %ray_dir_x, i32 0
%ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
%ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
- %ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
+ %ray_inv_dir0 = insertelement <3 x float> poison, float %ray_inv_dir_x, i32 0
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
@@ -411,13 +411,13 @@ main_body:
%node_ptr = load i32, ptr %gep_node_ptr, align 4
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
%ray_extent = load float, ptr %gep_ray, align 4
- %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
+ %ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
- %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
+ %ray_dir0 = insertelement <3 x float> poison, float 3.0, i32 0
%ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
%ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
- %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
+ %ray_inv_dir0 = insertelement <3 x float> poison, float 6.0, i32 0
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
@@ -559,13 +559,13 @@ main_body:
%node_ptr = load i32, ptr %gep_node_ptr, align 4
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
%ray_extent = load float, ptr %gep_ray, align 4
- %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
+ %ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
- %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
+ %ray_dir0 = insertelement <3 x half> poison, half 3.0, i32 0
%ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
%ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
- %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
+ %ray_inv_dir0 = insertelement <3 x half> poison, half 6.0, i32 0
%ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
%ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
@@ -720,13 +720,13 @@ main_body:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
%ray_extent = load float, ptr %gep_ray, align 4
- %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
+ %ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
- %ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
+ %ray_dir0 = insertelement <3 x float> poison, float 3.0, i32 0
%ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
%ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
- %ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
+ %ray_inv_dir0 = insertelement <3 x float> poison, float 6.0, i32 0
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
@@ -870,13 +870,13 @@ main_body:
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
%ray_extent = load float, ptr %gep_ray, align 4
- %ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
+ %ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
- %ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
+ %ray_dir0 = insertelement <3 x half> poison, half 3.0, i32 0
%ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
%ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
- %ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
+ %ray_inv_dir0 = insertelement <3 x half> poison, half 6.0, i32 0
%ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
%ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
index 2346cf0ba6303..33ef08273c8b5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll
@@ -58,7 +58,7 @@ entry:
%b.val = load <2 x i16>, ptr addrspace(1) %b.gep
%b.elt0 = extractelement <2 x i16> %b.val, i32 0
%b.elt1 = extractelement <2 x i16> %b.val, i32 1
- %b0 = insertelement <2 x i16> undef, i16 %b.elt1, i32 0
+ %b0 = insertelement <2 x i16> poison, i16 %b.elt1, i32 0
%b1 = insertelement <2 x i16> %b0, i16 %b.elt0, i32 1
%r.val = call i32 @llvm.amdgcn.udot2(<2 x i16> <i16 1, i16 1>, <2 x i16> %b1, i32 %c, i1 0)
store i32 %r.val, ptr addrspace(1) %r
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.pow.ll b/llvm/test/CodeGen/AMDGPU/llvm.pow.ll
index 88b0526b174b9..55c2ad3483c4c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.pow.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.pow.ll
@@ -9,7 +9,7 @@ define amdgpu_ps void @test1(<4 x float> inreg %reg0) {
%r0 = extractelement <4 x float> %reg0, i32 0
%r1 = extractelement <4 x float> %reg0, i32 1
%r2 = call float @llvm.pow.f32( float %r0, float %r1)
- %vec = insertelement <4 x float> undef, float %r2, i32 0
+ %vec = insertelement <4 x float> poison, float %r2, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.r600.cube.ll b/llvm/test/CodeGen/AMDGPU/llvm.r600.cube.ll
index 7ec7d9bdb400f..f471f4549823e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.r600.cube.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.r600.cube.ll
@@ -18,7 +18,7 @@ main_body:
%tmp8 = load <4 x float>, ptr addrspace(8) getelementptr ([1024 x <4 x float>], ptr addrspace(8) null, i64 0, i32 9)
%tmp9 = extractelement <4 x float> %tmp8, i32 2
%tmp10 = fdiv float %tmp9, %tmp1
- %tmp11 = insertelement <4 x float> undef, float %tmp4, i32 0
+ %tmp11 = insertelement <4 x float> poison, float %tmp4, i32 0
%tmp12 = insertelement <4 x float> %tmp11, float %tmp7, i32 1
%tmp13 = insertelement <4 x float> %tmp12, float %tmp10, i32 2
%tmp14 = insertelement <4 x float> %tmp13, float 1.000000e+00, i32 3
@@ -33,7 +33,7 @@ main_body:
%tmp23 = fadd float %tmp22, 1.500000e+00
%tmp24 = fmul float %tmp17, %tmp21
%tmp25 = fadd float %tmp24, 1.500000e+00
- %tmp26 = insertelement <4 x float> undef, float %tmp25, i32 0
+ %tmp26 = insertelement <4 x float> poison, float %tmp25, i32 0
%tmp27 = insertelement <4 x float> %tmp26, float %tmp23, i32 1
%tmp28 = insertelement <4 x float> %tmp27, float %tmp19, i32 2
%tmp29 = insertelement <4 x float> %tmp28, float %tmp25, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/load-hi16.ll b/llvm/test/CodeGen/AMDGPU/load-hi16.ll
index 0c61c58ef0619..c4eafe5d999a4 100644
--- a/llvm/test/CodeGen/AMDGPU/load-hi16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-hi16.ll
@@ -66,7 +66,7 @@ entry:
%load.lo = load i16, ptr addrspace(3) %in
%load.hi = load i16, ptr addrspace(3) %gep
store i16 %load.lo, ptr addrspace(3) null
- %build0 = insertelement <2 x i16> undef, i16 %load.lo, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %load.lo, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load.hi, i32 1
ret <2 x i16> %build1
}
@@ -133,7 +133,7 @@ entry:
%load.lo = load i16, ptr addrspace(3) %in
%load.hi = load i16, ptr addrspace(3) %gep
store i16 %load.hi, ptr addrspace(3) null
- %build0 = insertelement <2 x i16> undef, i16 %load.lo, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %load.lo, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load.hi, i32 1
ret <2 x i16> %build1
}
@@ -201,7 +201,7 @@ entry:
%load.hi = load i16, ptr addrspace(3) %gep
store i16 %load.lo, ptr addrspace(3) %out0
store i16 %load.hi, ptr addrspace(3) %out1
- %build0 = insertelement <2 x i16> undef, i16 %load.lo, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %load.lo, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load.hi, i32 1
ret <2 x i16> %build1
}
@@ -239,7 +239,7 @@ define <2 x i16> @load_local_hi_v2i16_undeflo(ptr addrspace(3) %in) #0 {
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, ptr addrspace(3) %in
- %build = insertelement <2 x i16> undef, i16 %load, i32 1
+ %build = insertelement <2 x i16> poison, i16 %load, i32 1
ret <2 x i16> %build
}
@@ -280,7 +280,7 @@ define <2 x i16> @load_local_hi_v2i16_reglo(ptr addrspace(3) %in, i16 %reg) #0 {
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, ptr addrspace(3) %in
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
ret <2 x i16> %build1
}
@@ -328,7 +328,7 @@ define void @load_local_hi_v2i16_reglo_vreg(ptr addrspace(3) %in, i16 %reg) #0 {
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, ptr addrspace(3) %in
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -459,7 +459,7 @@ define void @load_local_hi_v2f16_reglo_vreg(ptr addrspace(3) %in, half %reg) #0
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load half, ptr addrspace(3) %in
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -509,7 +509,7 @@ define void @load_local_hi_v2i16_reglo_vreg_zexti8(ptr addrspace(3) %in, i16 %re
entry:
%load = load i8, ptr addrspace(3) %in
%ext = zext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -559,7 +559,7 @@ define void @load_local_hi_v2i16_reglo_vreg_sexti8(ptr addrspace(3) %in, i16 %re
entry:
%load = load i8, ptr addrspace(3) %in
%ext = sext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -611,7 +611,7 @@ entry:
%ext = zext i8 %load to i16
%bitcast = bitcast i16 %ext to half
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %bitcast, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -663,7 +663,7 @@ entry:
%ext = sext i8 %load to i16
%bitcast = bitcast i16 %ext to half
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %bitcast, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -714,7 +714,7 @@ define void @load_global_hi_v2i16_reglo_vreg(ptr addrspace(1) %in, i16 %reg) #0
entry:
%gep = getelementptr inbounds i16, ptr addrspace(1) %in, i64 -2047
%load = load i16, ptr addrspace(1) %gep
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -765,7 +765,7 @@ define void @load_global_hi_v2f16_reglo_vreg(ptr addrspace(1) %in, half %reg) #0
entry:
%gep = getelementptr inbounds half, ptr addrspace(1) %in, i64 -2047
%load = load half, ptr addrspace(1) %gep
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -817,7 +817,7 @@ entry:
%gep = getelementptr inbounds i8, ptr addrspace(1) %in, i64 -4095
%load = load i8, ptr addrspace(1) %gep
%ext = zext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -869,7 +869,7 @@ entry:
%gep = getelementptr inbounds i8, ptr addrspace(1) %in, i64 -4095
%load = load i8, ptr addrspace(1) %gep
%ext = sext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -922,7 +922,7 @@ entry:
%load = load i8, ptr addrspace(1) %gep
%ext = sext i8 %load to i16
%bitcast = bitcast i16 %ext to half
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %bitcast, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -975,7 +975,7 @@ entry:
%load = load i8, ptr addrspace(1) %gep
%ext = zext i8 %load to i16
%bitcast = bitcast i16 %ext to half
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %bitcast, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -1023,7 +1023,7 @@ define void @load_flat_hi_v2i16_reglo_vreg(ptr %in, i16 %reg) #0 {
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, ptr %in
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -1071,7 +1071,7 @@ define void @load_flat_hi_v2f16_reglo_vreg(ptr %in, half %reg) #0 {
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load half, ptr %in
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -1120,7 +1120,7 @@ define void @load_flat_hi_v2i16_reglo_vreg_zexti8(ptr %in, i16 %reg) #0 {
entry:
%load = load i8, ptr %in
%ext = zext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -1169,7 +1169,7 @@ define void @load_flat_hi_v2i16_reglo_vreg_sexti8(ptr %in, i16 %reg) #0 {
entry:
%load = load i8, ptr %in
%ext = sext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -1219,7 +1219,7 @@ entry:
%load = load i8, ptr %in
%ext = zext i8 %load to i16
%bitcast = bitcast i16 %ext to half
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %bitcast, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -1269,7 +1269,7 @@ entry:
%load = load i8, ptr %in
%ext = sext i8 %load to i16
%bitcast = bitcast i16 %ext to half
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %bitcast, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -1318,7 +1318,7 @@ define void @load_private_hi_v2i16_reglo_vreg(ptr addrspace(5) byval(i16) %in, i
entry:
%gep = getelementptr inbounds i16, ptr addrspace(5) %in, i64 2047
%load = load i16, ptr addrspace(5) %gep
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -1367,7 +1367,7 @@ define void @load_private_hi_v2f16_reglo_vreg(ptr addrspace(5) byval(half) %in,
entry:
%gep = getelementptr inbounds half, ptr addrspace(5) %in, i64 2047
%load = load half, ptr addrspace(5) %gep
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -1416,7 +1416,7 @@ define void @load_private_hi_v2i16_reglo_vreg_nooff(ptr addrspace(5) byval(i16)
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load volatile i16, ptr addrspace(5) inttoptr (i32 4094 to ptr addrspace(5))
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -1465,7 +1465,7 @@ define void @load_private_hi_v2f16_reglo_vreg_nooff(ptr addrspace(5) %in, half %
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load volatile half, ptr addrspace(5) inttoptr (i32 4094 to ptr addrspace(5))
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -1515,7 +1515,7 @@ entry:
%gep = getelementptr inbounds i8, ptr addrspace(5) %in, i64 4095
%load = load i8, ptr addrspace(5) %gep
%ext = zext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -1566,7 +1566,7 @@ entry:
%load = load i8, ptr addrspace(5) %gep
%ext = zext i8 %load to i16
%bitcast = bitcast i16 %ext to half
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %bitcast, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -1617,7 +1617,7 @@ entry:
%load = load i8, ptr addrspace(5) %gep
%ext = sext i8 %load to i16
%bitcast = bitcast i16 %ext to half
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %bitcast, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -1667,7 +1667,7 @@ entry:
%gep = getelementptr inbounds i8, ptr addrspace(5) %in, i64 4095
%load = load i8, ptr addrspace(5) %gep
%ext = sext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -1717,7 +1717,7 @@ define void @load_private_hi_v2i16_reglo_vreg_nooff_zexti8(ptr addrspace(5) %in,
entry:
%load = load volatile i8, ptr addrspace(5) inttoptr (i32 4094 to ptr addrspace(5))
%ext = zext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -1767,7 +1767,7 @@ define void @load_private_hi_v2i16_reglo_vreg_nooff_sexti8(ptr addrspace(5) %in,
entry:
%load = load volatile i8, ptr addrspace(5) inttoptr (i32 4094 to ptr addrspace(5))
%ext = sext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -1818,7 +1818,7 @@ entry:
%load = load volatile i8, ptr addrspace(5) inttoptr (i32 4094 to ptr addrspace(5))
%ext = zext i8 %load to i16
%bc.ext = bitcast i16 %ext to half
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %bc.ext, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -1869,7 +1869,7 @@ define void @load_constant_hi_v2i16_reglo_vreg(ptr addrspace(4) %in, i16 %reg) #
entry:
%gep = getelementptr inbounds i16, ptr addrspace(4) %in, i64 -2047
%load = load i16, ptr addrspace(4) %gep
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -1920,7 +1920,7 @@ define void @load_constant_hi_v2f16_reglo_vreg(ptr addrspace(4) %in, half %reg)
entry:
%gep = getelementptr inbounds half, ptr addrspace(4) %in, i64 -2047
%load = load half, ptr addrspace(4) %gep
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -1973,7 +1973,7 @@ entry:
%load = load i8, ptr addrspace(4) %gep
%ext = sext i8 %load to i16
%bitcast = bitcast i16 %ext to half
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %bitcast, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -2026,7 +2026,7 @@ entry:
%load = load i8, ptr addrspace(4) %gep
%ext = zext i8 %load to i16
%bitcast = bitcast i16 %ext to half
- %build0 = insertelement <2 x half> undef, half %reg, i32 0
+ %build0 = insertelement <2 x half> poison, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %bitcast, i32 1
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -2092,7 +2092,7 @@ entry:
store volatile i32 123, ptr addrspace(5) %obj0
%gep = getelementptr inbounds [4096 x i16], ptr addrspace(5) %obj1, i32 0, i32 2027
%load = load i16, ptr addrspace(5) %gep
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -2156,7 +2156,7 @@ entry:
%gep = getelementptr inbounds [4096 x i8], ptr addrspace(5) %obj1, i32 0, i32 4055
%load = load i8, ptr addrspace(5) %gep
%ext = sext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -2220,7 +2220,7 @@ entry:
%gep = getelementptr inbounds [4096 x i8], ptr addrspace(5) %obj1, i32 0, i32 4055
%load = load i8, ptr addrspace(5) %gep
%ext = zext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -2273,7 +2273,7 @@ entry:
%gep = getelementptr inbounds i16, ptr addrspace(3) %in, i32 1
%load0 = load volatile i16, ptr addrspace(3) %in
%load1 = load volatile i16, ptr addrspace(3) %gep
- %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %load0, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
ret <2 x i16> %build1
}
@@ -2324,7 +2324,7 @@ entry:
%gep = getelementptr inbounds i16, ptr addrspace(3) %in, i32 8
%load.lo = load i16, ptr addrspace(3) %in
%load.hi = load i16, ptr addrspace(3) %gep
- %build0 = insertelement <2 x i16> undef, i16 %load.lo, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %load.lo, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load.hi, i32 1
ret <2 x i16> %build1
}
@@ -2370,7 +2370,7 @@ define <2 x i16> @load_local_v2i16_broadcast(ptr addrspace(3) %in) #0 {
entry:
%gep = getelementptr inbounds i16, ptr addrspace(3) %in, i32 1
%load0 = load i16, ptr addrspace(3) %in
- %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %load0, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load0, i32 1
ret <2 x i16> %build1
}
@@ -2429,7 +2429,7 @@ entry:
%load.lo = load i16, ptr addrspace(3) %in
store i16 123, ptr addrspace(3) %may.alias
%load.hi = load i16, ptr addrspace(3) %gep
- %build0 = insertelement <2 x i16> undef, i16 %load.lo, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %load.lo, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load.hi, i32 1
ret <2 x i16> %build1
}
@@ -2483,7 +2483,7 @@ entry:
%gep = getelementptr inbounds i16, ptr addrspace(1) %in, i64 1
%load0 = load volatile i16, ptr addrspace(1) %in
%load1 = load volatile i16, ptr addrspace(1) %gep
- %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %load0, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
ret <2 x i16> %build1
}
@@ -2538,7 +2538,7 @@ entry:
%gep = getelementptr inbounds i16, ptr %in, i64 1
%load0 = load volatile i16, ptr %in
%load1 = load volatile i16, ptr %gep
- %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %load0, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
ret <2 x i16> %build1
}
@@ -2590,7 +2590,7 @@ entry:
%gep = getelementptr inbounds i16, ptr addrspace(4) %in, i64 1
%load0 = load volatile i16, ptr addrspace(4) %in
%load1 = load volatile i16, ptr addrspace(4) %gep
- %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %load0, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
ret <2 x i16> %build1
}
@@ -2641,7 +2641,7 @@ entry:
%gep = getelementptr inbounds i16, ptr addrspace(5) %in, i32 1
%load0 = load volatile i16, ptr addrspace(5) %in
%load1 = load volatile i16, ptr addrspace(5) %gep
- %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %load0, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
ret <2 x i16> %build1
}
@@ -2698,7 +2698,7 @@ define <2 x i16> @load_local_hi_v2i16_store_local_lo(i16 %reg, ptr addrspace(3)
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, ptr addrspace(3) %in
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store volatile i16 %reg, ptr addrspace(3) %in
ret <2 x i16> %build1
diff --git a/llvm/test/CodeGen/AMDGPU/load-input-fold.ll b/llvm/test/CodeGen/AMDGPU/load-input-fold.ll
index a243e6f538722..7d34f6b4abfbd 100644
--- a/llvm/test/CodeGen/AMDGPU/load-input-fold.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-input-fold.ll
@@ -80,16 +80,16 @@ main_body:
%75 = extractelement <4 x float> %74, i32 1
%76 = load <4 x float>, ptr addrspace(8) getelementptr ([1024 x <4 x float>], ptr addrspace(8) null, i64 0, i32 4)
%77 = extractelement <4 x float> %76, i32 2
- %78 = insertelement <4 x float> undef, float %4, i32 0
+ %78 = insertelement <4 x float> poison, float %4, i32 0
%79 = insertelement <4 x float> %78, float %5, i32 1
%80 = insertelement <4 x float> %79, float %6, i32 2
%81 = insertelement <4 x float> %80, float 0.000000e+00, i32 3
- %82 = insertelement <4 x float> undef, float %73, i32 0
+ %82 = insertelement <4 x float> poison, float %73, i32 0
%83 = insertelement <4 x float> %82, float %75, i32 1
%84 = insertelement <4 x float> %83, float %77, i32 2
%85 = insertelement <4 x float> %84, float 0.000000e+00, i32 3
%86 = call float @llvm.r600.dot4(<4 x float> %81, <4 x float> %85)
- %87 = insertelement <4 x float> undef, float %86, i32 0
+ %87 = insertelement <4 x float> poison, float %86, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %87, i32 2, i32 2)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/load-lo16.ll b/llvm/test/CodeGen/AMDGPU/load-lo16.ll
index 3ef86c13e150a..ab1ca9093b551 100644
--- a/llvm/test/CodeGen/AMDGPU/load-lo16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-lo16.ll
@@ -28,7 +28,7 @@ define <2 x i16> @load_local_lo_v2i16_undeflo(ptr addrspace(3) %in) #0 {
; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, ptr addrspace(3) %in
- %build = insertelement <2 x i16> undef, i16 %load, i32 0
+ %build = insertelement <2 x i16> poison, i16 %load, i32 0
ret <2 x i16> %build
}
@@ -71,7 +71,7 @@ define <2 x i16> @load_local_lo_v2i16_reglo(ptr addrspace(3) %in, i16 %reg) #0 {
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, ptr addrspace(3) %in
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 1
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 1
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 0
ret <2 x i16> %build1
}
@@ -124,7 +124,7 @@ define void @load_local_lo_v2i16_reglo_vreg(ptr addrspace(3) %in, i16 %reg) #0 {
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, ptr addrspace(3) %in
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 1
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 1
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 0
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -282,7 +282,7 @@ define void @load_local_lo_v2f16_reglo_vreg(ptr addrspace(3) %in, half %reg) #0
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load half, ptr addrspace(3) %in
- %build0 = insertelement <2 x half> undef, half %reg, i32 1
+ %build0 = insertelement <2 x half> poison, half %reg, i32 1
%build1 = insertelement <2 x half> %build0, half %load, i32 0
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -377,7 +377,7 @@ define void @load_local_lo_v2i16_reglo_vreg_zexti8(ptr addrspace(3) %in, i16 %re
entry:
%load = load i8, ptr addrspace(3) %in
%ext = zext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 1
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 1
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 0
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -472,7 +472,7 @@ define void @load_local_lo_v2i16_reglo_vreg_sexti8(ptr addrspace(3) %in, i16 %re
entry:
%load = load i8, ptr addrspace(3) %in
%ext = sext i8 %load to i16
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 1
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 1
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 0
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
@@ -527,7 +527,7 @@ entry:
%load = load i8, ptr addrspace(3) %in
%ext = zext i8 %load to i16
%bitcast = bitcast i16 %ext to half
- %build0 = insertelement <2 x half> undef, half %reg, i32 1
+ %build0 = insertelement <2 x half> poison, half %reg, i32 1
%build1 = insertelement <2 x half> %build0, half %bitcast, i32 0
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -582,7 +582,7 @@ entry:
%load = load i8, ptr addrspace(3) %in
%ext = sext i8 %load to i16
%bitcast = bitcast i16 %ext to half
- %build0 = insertelement <2 x half> undef, half %reg, i32 1
+ %build0 = insertelement <2 x half> poison, half %reg, i32 1
%build1 = insertelement <2 x half> %build0, half %bitcast, i32 0
store <2 x half> %build1, ptr addrspace(1) undef
ret void
@@ -1363,7 +1363,7 @@ define void @load_private_lo_v2i16_reghi_vreg(ptr addrspace(5) byval(i16) %in, i
entry:
%gep = getelementptr inbounds i16, ptr addrspace(5) %in, i64 2047
%load = load i16, ptr addrspace(5) %gep
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 1
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 1
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 0
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll b/llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
index 2d3c03bbe5317..9c8aad177db65 100644
--- a/llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
+++ b/llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll
@@ -35,7 +35,7 @@ bb1: ; preds = %bb3, %bb
%i2 = extractelement <3 x float> %i, i64 2
%i3 = fmul float %i2, 1.000000e+00
%i4 = fmul nsz <3 x float> %arg, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00>
- %i5 = insertelement <3 x float> undef, float %i3, i32 0
+ %i5 = insertelement <3 x float> poison, float %i3, i32 0
%i6 = shufflevector <3 x float> %i5, <3 x float> undef, <3 x i32> zeroinitializer
%i7 = fmul <3 x float> %i4, %i6
%i8 = fcmp oeq float %i3, 0.000000e+00
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
index 989ef6f981d9d..018cdee038b91 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
@@ -58,7 +58,7 @@ define amdgpu_kernel void @workgroup_ids_kernel() {
%idx = call i32 @llvm.amdgcn.workgroup.id.x()
%idy = call i32 @llvm.amdgcn.workgroup.id.y()
%idz = call i32 @llvm.amdgcn.workgroup.id.z()
- %ielemx = insertelement <3 x i32> undef, i32 %idx, i64 0
+ %ielemx = insertelement <3 x i32> poison, i32 %idx, i64 0
%ielemy = insertelement <3 x i32> %ielemx, i32 %idy, i64 1
%ielemz = insertelement <3 x i32> %ielemy, i32 %idz, i64 2
call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %ielemz, ptr addrspace(8) undef, i32 0, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
index 356439bad8f00..dcec7288686b1 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
@@ -65,7 +65,7 @@ define amdgpu_cs void @_amdgpu_cs_main() {
%idx = call i32 @llvm.amdgcn.workgroup.id.x()
%idy = call i32 @llvm.amdgcn.workgroup.id.y()
%idz = call i32 @llvm.amdgcn.workgroup.id.z()
- %ielemx = insertelement <3 x i32> undef, i32 %idx, i64 0
+ %ielemx = insertelement <3 x i32> poison, i32 %idx, i64 0
%ielemy = insertelement <3 x i32> %ielemx, i32 %idy, i64 1
%ielemz = insertelement <3 x i32> %ielemy, i32 %idz, i64 2
call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %ielemz, ptr addrspace(8) undef, i32 0, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
index a7060e4f198f1..4fffab84a29db 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
@@ -55,7 +55,7 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo(half %src0, half %s
%src2.ext = fpext half %src2 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
%cvt.result = fptrunc float %result to half
- %vec.result = insertelement <2 x half> undef, half %cvt.result, i32 1
+ %vec.result = insertelement <2 x half> poison, half %cvt.result, i32 1
ret <2 x half> %vec.result
}
@@ -112,7 +112,7 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_constlo(half %src0, half %s
%src2.ext = fpext half %src2 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
%cvt.result = fptrunc float %result to half
- %vec.result = insertelement <2 x half> <half 1.0, half undef>, half %cvt.result, i32 1
+ %vec.result = insertelement <2 x half> <half 1.0, half poison>, half %cvt.result, i32 1
ret <2 x half> %vec.result
}
@@ -167,7 +167,7 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_reglo(half %src0, half %src
%src2.ext = fpext half %src2 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
%cvt.result = fptrunc float %result to half
- %vec = insertelement <2 x half> undef, half %lo, i32 0
+ %vec = insertelement <2 x half> poison, half %lo, i32 0
%vec.result = insertelement <2 x half> %vec, half %cvt.result, i32 1
ret <2 x half> %vec.result
}
@@ -398,7 +398,7 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %
%max = call float @llvm.maxnum.f32(float %result, float 0.0)
%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
%cvt.result = fptrunc float %clamp to half
- %vec.result = insertelement <2 x half> undef, half %cvt.result, i32 1
+ %vec.result = insertelement <2 x half> poison, half %cvt.result, i32 1
ret <2 x half> %vec.result
}
@@ -457,7 +457,7 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt(half
%cvt.result = fptrunc float %result to half
%max = call half @llvm.maxnum.f16(half %cvt.result, half 0.0)
%clamp = call half @llvm.minnum.f16(half %max, half 1.0)
- %vec.result = insertelement <2 x half> undef, half %clamp, i32 1
+ %vec.result = insertelement <2 x half> poison, half %clamp, i32 1
ret <2 x half> %vec.result
}
@@ -534,7 +534,7 @@ define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi
store volatile half %cvt.result, ptr addrspace(1) undef
%max = call half @llvm.maxnum.f16(half %cvt.result, half 0.0)
%clamp = call half @llvm.minnum.f16(half %max, half 1.0)
- %vec.result = insertelement <2 x half> undef, half %clamp, i32 1
+ %vec.result = insertelement <2 x half> poison, half %clamp, i32 1
ret <2 x half> %vec.result
}
diff --git a/llvm/test/CodeGen/AMDGPU/mad_uint24.ll b/llvm/test/CodeGen/AMDGPU/mad_uint24.ll
index a71b083d22e2b..99d930bf73fc9 100644
--- a/llvm/test/CodeGen/AMDGPU/mad_uint24.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad_uint24.ll
@@ -298,7 +298,7 @@ bb19: ; preds = %bb19, %bb
%tmp39 = mul i32 %tmp38, %tmp
%tmp40 = add i32 %tmp39, %arg5
store i32 %tmp40, ptr addrspace(1) %arg7
- %tmp41 = insertelement <4 x i32> undef, i32 %tmp40, i32 0
+ %tmp41 = insertelement <4 x i32> poison, i32 %tmp40, i32 0
%tmp42 = and i32 %tmp29, 16777215
%tmp43 = mul i32 %tmp42, %tmp11
%tmp44 = add i32 %tmp43, %tmp10
diff --git a/llvm/test/CodeGen/AMDGPU/max-literals.ll b/llvm/test/CodeGen/AMDGPU/max-literals.ll
index f1cbf43aa089a..2cfe9d528b66f 100644
--- a/llvm/test/CodeGen/AMDGPU/max-literals.ll
+++ b/llvm/test/CodeGen/AMDGPU/max-literals.ll
@@ -17,14 +17,14 @@ main_body:
%9 = bitcast float %4 to i32
%10 = mul i32 %9, 6
%11 = bitcast i32 %10 to float
- %12 = insertelement <4 x float> undef, float %5, i32 0
+ %12 = insertelement <4 x float> poison, float %5, i32 0
%13 = insertelement <4 x float> %12, float %6, i32 1
%14 = insertelement <4 x float> %13, float %7, i32 2
%15 = insertelement <4 x float> %14, float %8, i32 3
%16 = insertelement <4 x float> %15, float %11, i32 3
%17 = call float @llvm.r600.dot4(<4 x float> %15,<4 x float> %16)
- %18 = insertelement <4 x float> undef, float %17, i32 0
+ %18 = insertelement <4 x float> poison, float %17, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %18, i32 0, i32 2)
ret void
}
@@ -46,14 +46,14 @@ main_body:
%9 = bitcast float %4 to i32
%10 = mul i32 %9, 6
%11 = bitcast i32 %10 to float
- %12 = insertelement <4 x float> undef, float %5, i32 0
+ %12 = insertelement <4 x float> poison, float %5, i32 0
%13 = insertelement <4 x float> %12, float %6, i32 1
%14 = insertelement <4 x float> %13, float %7, i32 2
%15 = insertelement <4 x float> %14, float %8, i32 3
%16 = insertelement <4 x float> %15, float %11, i32 3
%17 = call float @llvm.r600.dot4(<4 x float> %15,<4 x float> %16)
- %18 = insertelement <4 x float> undef, float %17, i32 0
+ %18 = insertelement <4 x float> poison, float %17, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %18, i32 0, i32 2)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/memory_clause.ll b/llvm/test/CodeGen/AMDGPU/memory_clause.ll
index 15f31b4e86dbe..1324951d06334 100644
--- a/llvm/test/CodeGen/AMDGPU/memory_clause.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory_clause.ll
@@ -328,10 +328,10 @@ entry:
%gep = getelementptr inbounds i16, ptr addrspace(1) %in, i64 32
%load1 = load i16, ptr addrspace(1) %in
%load2 = load i16, ptr addrspace(1) %gep
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
store <2 x i16> %build1, ptr addrspace(1) %out
- %build2 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build2 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build3 = insertelement <2 x i16> %build2, i16 %load2, i32 1
%gep2 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i64 32
store <2 x i16> %build3, ptr addrspace(1) %gep2
diff --git a/llvm/test/CodeGen/AMDGPU/merge-store-crash.ll b/llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
index bcd80a2a03b05..0809891aec72b 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
@@ -22,10 +22,10 @@ main_body:
%tmp5 = getelementptr [8192 x i32], ptr addrspace(3) @tess_lds, i64 0, i64 %tmp4
store float %tmp1, ptr addrspace(3) %tmp5, align 4
%tmp7 = bitcast float %tmp1 to i32
- %tmp8 = insertelement <4 x i32> undef, i32 %tmp2, i32 0
+ %tmp8 = insertelement <4 x i32> poison, i32 %tmp2, i32 0
%tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp7, i32 1
- %tmp10 = insertelement <4 x i32> %tmp9, i32 undef, i32 2
- %tmp11 = insertelement <4 x i32> %tmp10, i32 undef, i32 3
+ %tmp10 = insertelement <4 x i32> %tmp9, i32 poison, i32 2
+ %tmp11 = insertelement <4 x i32> %tmp10, i32 poison, i32 3
call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %tmp11, ptr addrspace(8) undef, i32 0, i32 0, i32 %arg, i32 78, i32 3) #2
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
index 4a635d6e7f59f..d2835f06d8e0e 100644
--- a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll
@@ -264,7 +264,7 @@ define amdgpu_kernel void @test_mfma_loop_vgpr_init(ptr addrspace(1) %arg) #0 {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%init = bitcast i32 %tid to float
- %tmp0 = insertelement <32 x float> undef, float %init, i32 0
+ %tmp0 = insertelement <32 x float> poison, float %init, i32 0
%tmp1 = insertelement <32 x float> %tmp0, float %init, i32 1
%tmp2 = insertelement <32 x float> %tmp1, float %init, i32 2
%tmp3 = insertelement <32 x float> %tmp2, float %init, i32 3
@@ -332,7 +332,7 @@ exit:
define amdgpu_kernel void @test_mfma_loop_sgpr_init(ptr addrspace(1) %arg, float %init) #0 {
entry:
- %tmp0 = insertelement <32 x float> undef, float %init, i32 0
+ %tmp0 = insertelement <32 x float> poison, float %init, i32 0
%tmp1 = insertelement <32 x float> %tmp0, float %init, i32 1
%tmp2 = insertelement <32 x float> %tmp1, float %init, i32 2
%tmp3 = insertelement <32 x float> %tmp2, float %init, i32 3
@@ -527,7 +527,7 @@ define amdgpu_kernel void @test_mfma_loop_agpr_init(ptr addrspace(1) %arg) #0 {
entry:
%mai.0 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.0, float 2.0, <32 x float> zeroinitializer, i32 0, i32 0, i32 0)
%init = extractelement <32 x float> %mai.0, i32 0
- %tmp0 = insertelement <32 x float> undef, float %init, i32 0
+ %tmp0 = insertelement <32 x float> poison, float %init, i32 0
%tmp1 = insertelement <32 x float> %tmp0, float %init, i32 1
%tmp2 = insertelement <32 x float> %tmp1, float %init, i32 2
%tmp3 = insertelement <32 x float> %tmp2, float %init, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/nsa-reassign.ll b/llvm/test/CodeGen/AMDGPU/nsa-reassign.ll
index 6df702d61602a..ff80af3d700ba 100644
--- a/llvm/test/CodeGen/AMDGPU/nsa-reassign.ll
+++ b/llvm/test/CodeGen/AMDGPU/nsa-reassign.ll
@@ -15,7 +15,7 @@ main_body:
%lod.1 = fadd float %lod, 1.0
%v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare.1, float %s1.1, float %t1.1, float %r1.1, float %lod.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
- %r.0 = insertelement <2 x float> undef, float %v1, i32 0
+ %r.0 = insertelement <2 x float> poison, float %v1, i32 0
%r = insertelement <2 x float> %r.0, float %v2, i32 1
ret <2 x float> %r
}
@@ -35,7 +35,7 @@ main_body:
%lod.1 = fadd float %lod, 1.0
%v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare.1, float %s1.1, float %t1.1, float %r1.1, float %lod.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
- %r.0 = insertelement <2 x float> undef, float %v1, i32 0
+ %r.0 = insertelement <2 x float> poison, float %v1, i32 0
%r = insertelement <2 x float> %r.0, float %v2, i32 1
ret <2 x float> %r
}
@@ -55,7 +55,7 @@ main_body:
%lod.1 = fadd float %lod, 1.0
%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
%v1 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %t2.1, float %s2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
- %r.0 = insertelement <2 x float> undef, float %v1, i32 0
+ %r.0 = insertelement <2 x float> poison, float %v1, i32 0
%r = insertelement <2 x float> %r.0, float %v2, i32 1
ret <2 x float> %r
}
@@ -75,7 +75,7 @@ main_body:
%lod.1 = fadd float %lod, 1.0
%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 1)
%v1 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
- %r.0 = insertelement <2 x float> undef, float %v1, i32 0
+ %r.0 = insertelement <2 x float> poison, float %v1, i32 0
%r = insertelement <2 x float> %r.0, float %v2, i32 1
ret <2 x float> %r
}
diff --git a/llvm/test/CodeGen/AMDGPU/operand-folding.ll b/llvm/test/CodeGen/AMDGPU/operand-folding.ll
index 1e3299a023736..040f53fdf66bb 100644
--- a/llvm/test/CodeGen/AMDGPU/operand-folding.ll
+++ b/llvm/test/CodeGen/AMDGPU/operand-folding.ll
@@ -68,7 +68,7 @@ entry:
%tmp1 = add i32 %tmp0, 1
%tmp2 = add i32 %tmp0, 2
%tmp3 = add i32 %tmp0, 3
- %vec0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
+ %vec0 = insertelement <4 x i32> poison, i32 %tmp0, i32 0
%vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1
%vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2
%vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
@@ -100,7 +100,7 @@ entry:
%tmp1 = add i32 %tmp0, 1
%tmp2 = add i32 %tmp0, 2
%tmp3 = add i32 %tmp0, 3
- %vec0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
+ %vec0 = insertelement <4 x i32> poison, i32 %tmp0, i32 0
%vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1
%vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2
%vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/pack.v2f16.ll b/llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
index da6120812ac1d..ef9305e1fc358 100644
--- a/llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/pack.v2f16.ll
@@ -53,7 +53,7 @@ define amdgpu_kernel void @s_pack_v2f16(ptr addrspace(4) %in0, ptr addrspace(4)
%hi.i = trunc i32 %val1 to i16
%lo = bitcast i16 %lo.i to half
%hi = bitcast i16 %hi.i to half
- %vec.0 = insertelement <2 x half> undef, half %lo, i32 0
+ %vec.0 = insertelement <2 x half> poison, half %lo, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half %hi, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
@@ -102,7 +102,7 @@ define amdgpu_kernel void @s_pack_v2f16_imm_lo(ptr addrspace(4) %in1) #0 {
%val1 = load i32, ptr addrspace(4) %in1
%hi.i = trunc i32 %val1 to i16
%hi = bitcast i16 %hi.i to half
- %vec.0 = insertelement <2 x half> undef, half 0xH1234, i32 0
+ %vec.0 = insertelement <2 x half> poison, half 0xH1234, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half %hi, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
@@ -151,7 +151,7 @@ define amdgpu_kernel void @s_pack_v2f16_imm_hi(ptr addrspace(4) %in0) #0 {
%val0 = load i32, ptr addrspace(4) %in0
%lo.i = trunc i32 %val0 to i16
%lo = bitcast i16 %lo.i to half
- %vec.0 = insertelement <2 x half> undef, half %lo, i32 0
+ %vec.0 = insertelement <2 x half> poison, half %lo, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half 0xH1234, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
@@ -230,7 +230,7 @@ define amdgpu_kernel void @v_pack_v2f16(ptr addrspace(1) %in0, ptr addrspace(1)
%hi.i = trunc i32 %val1 to i16
%lo = bitcast i16 %lo.i to half
%hi = bitcast i16 %hi.i to half
- %vec.0 = insertelement <2 x half> undef, half %lo, i32 0
+ %vec.0 = insertelement <2 x half> poison, half %lo, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half %hi, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
@@ -313,7 +313,7 @@ define amdgpu_kernel void @v_pack_v2f16_user(ptr addrspace(1) %in0, ptr addrspac
%hi.i = trunc i32 %val1 to i16
%lo = bitcast i16 %lo.i to half
%hi = bitcast i16 %hi.i to half
- %vec.0 = insertelement <2 x half> undef, half %lo, i32 0
+ %vec.0 = insertelement <2 x half> poison, half %lo, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half %hi, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
%foo = add i32 %vec.i32, 9
@@ -376,7 +376,7 @@ define amdgpu_kernel void @v_pack_v2f16_imm_lo(ptr addrspace(1) %in1) #0 {
%val1 = load volatile i32, ptr addrspace(1) %in1.gep
%hi.i = trunc i32 %val1 to i16
%hi = bitcast i16 %hi.i to half
- %vec.0 = insertelement <2 x half> undef, half 0xH1234, i32 0
+ %vec.0 = insertelement <2 x half> poison, half 0xH1234, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half %hi, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
@@ -438,7 +438,7 @@ define amdgpu_kernel void @v_pack_v2f16_inline_imm_lo(ptr addrspace(1) %in1) #0
%val1 = load volatile i32, ptr addrspace(1) %in1.gep
%hi.i = trunc i32 %val1 to i16
%hi = bitcast i16 %hi.i to half
- %vec.0 = insertelement <2 x half> undef, half 4.0, i32 0
+ %vec.0 = insertelement <2 x half> poison, half 4.0, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half %hi, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
@@ -500,7 +500,7 @@ define amdgpu_kernel void @v_pack_v2f16_imm_hi(ptr addrspace(1) %in0) #0 {
%val0 = load volatile i32, ptr addrspace(1) %in0.gep
%lo.i = trunc i32 %val0 to i16
%lo = bitcast i16 %lo.i to half
- %vec.0 = insertelement <2 x half> undef, half %lo, i32 0
+ %vec.0 = insertelement <2 x half> poison, half %lo, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half 0xH1234, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
@@ -562,7 +562,7 @@ define amdgpu_kernel void @v_pack_v2f16_inline_f16imm_hi(ptr addrspace(1) %in0)
%val0 = load volatile i32, ptr addrspace(1) %in0.gep
%lo.i = trunc i32 %val0 to i16
%lo = bitcast i16 %lo.i to half
- %vec.0 = insertelement <2 x half> undef, half %lo, i32 0
+ %vec.0 = insertelement <2 x half> poison, half %lo, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half 1.0, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
@@ -623,7 +623,7 @@ define amdgpu_kernel void @v_pack_v2f16_inline_imm_hi(ptr addrspace(1) %in0) #0
%val0 = load volatile i32, ptr addrspace(1) %in0.gep
%lo.i = trunc i32 %val0 to i16
%lo = bitcast i16 %lo.i to half
- %vec.0 = insertelement <2 x half> undef, half %lo, i32 0
+ %vec.0 = insertelement <2 x half> poison, half %lo, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half 0xH0040, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
diff --git a/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll b/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
index 44128f0e0dcd8..e706661e2f199 100644
--- a/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
@@ -51,7 +51,7 @@ define amdgpu_kernel void @s_pack_v2i16(ptr addrspace(4) %in0, ptr addrspace(4)
%val1 = load volatile i32, ptr addrspace(4) %in1
%lo = trunc i32 %val0 to i16
%hi = trunc i32 %val1 to i16
- %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
+ %vec.0 = insertelement <2 x i16> poison, i16 %lo, i32 0
%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
%vec.i32 = bitcast <2 x i16> %vec.1 to i32
@@ -99,7 +99,7 @@ define amdgpu_kernel void @s_pack_v2i16_imm_lo(ptr addrspace(4) %in1) #0 {
; GFX7-NEXT: s_endpgm
%val1 = load i32, ptr addrspace(4) %in1
%hi = trunc i32 %val1 to i16
- %vec.0 = insertelement <2 x i16> undef, i16 456, i32 0
+ %vec.0 = insertelement <2 x i16> poison, i16 456, i32 0
%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
%vec.i32 = bitcast <2 x i16> %vec.1 to i32
@@ -147,7 +147,7 @@ define amdgpu_kernel void @s_pack_v2i16_imm_hi(ptr addrspace(4) %in0) #0 {
; GFX7-NEXT: s_endpgm
%val0 = load i32, ptr addrspace(4) %in0
%lo = trunc i32 %val0 to i16
- %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
+ %vec.0 = insertelement <2 x i16> poison, i16 %lo, i32 0
%vec.1 = insertelement <2 x i16> %vec.0, i16 456, i32 1
%vec.i32 = bitcast <2 x i16> %vec.1 to i32
@@ -224,7 +224,7 @@ define amdgpu_kernel void @v_pack_v2i16(ptr addrspace(1) %in0, ptr addrspace(1)
%val1 = load volatile i32, ptr addrspace(1) %in1.gep
%lo = trunc i32 %val0 to i16
%hi = trunc i32 %val1 to i16
- %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
+ %vec.0 = insertelement <2 x i16> poison, i16 %lo, i32 0
%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
%vec.i32 = bitcast <2 x i16> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
@@ -305,7 +305,7 @@ define amdgpu_kernel void @v_pack_v2i16_user(ptr addrspace(1) %in0, ptr addrspac
%val1 = load volatile i32, ptr addrspace(1) %in1.gep
%lo = trunc i32 %val0 to i16
%hi = trunc i32 %val1 to i16
- %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
+ %vec.0 = insertelement <2 x i16> poison, i16 %lo, i32 0
%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
%vec.i32 = bitcast <2 x i16> %vec.1 to i32
%foo = add i32 %vec.i32, 9
@@ -367,7 +367,7 @@ define amdgpu_kernel void @v_pack_v2i16_imm_lo(ptr addrspace(1) %in1) #0 {
%in1.gep = getelementptr inbounds i32, ptr addrspace(1) %in1, i64 %tid.ext
%val1 = load volatile i32, ptr addrspace(1) %in1.gep
%hi = trunc i32 %val1 to i16
- %vec.0 = insertelement <2 x i16> undef, i16 123, i32 0
+ %vec.0 = insertelement <2 x i16> poison, i16 123, i32 0
%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
%vec.i32 = bitcast <2 x i16> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
@@ -427,7 +427,7 @@ define amdgpu_kernel void @v_pack_v2i16_inline_imm_lo(ptr addrspace(1) %in1) #0
%in1.gep = getelementptr inbounds i32, ptr addrspace(1) %in1, i64 %tid.ext
%val1 = load volatile i32, ptr addrspace(1) %in1.gep
%hi = trunc i32 %val1 to i16
- %vec.0 = insertelement <2 x i16> undef, i16 64, i32 0
+ %vec.0 = insertelement <2 x i16> poison, i16 64, i32 0
%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
%vec.i32 = bitcast <2 x i16> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
@@ -488,7 +488,7 @@ define amdgpu_kernel void @v_pack_v2i16_imm_hi(ptr addrspace(1) %in0) #0 {
%in0.gep = getelementptr inbounds i32, ptr addrspace(1) %in0, i64 %tid.ext
%val0 = load volatile i32, ptr addrspace(1) %in0.gep
%lo = trunc i32 %val0 to i16
- %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
+ %vec.0 = insertelement <2 x i16> poison, i16 %lo, i32 0
%vec.1 = insertelement <2 x i16> %vec.0, i16 123, i32 1
%vec.i32 = bitcast <2 x i16> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
@@ -548,7 +548,7 @@ define amdgpu_kernel void @v_pack_v2i16_inline_imm_hi(ptr addrspace(1) %in0) #0
%in0.gep = getelementptr inbounds i32, ptr addrspace(1) %in0, i64 %tid.ext
%val0 = load volatile i32, ptr addrspace(1) %in0.gep
%lo = trunc i32 %val0 to i16
- %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
+ %vec.0 = insertelement <2 x i16> poison, i16 %lo, i32 0
%vec.1 = insertelement <2 x i16> %vec.0, i16 7, i32 1
%vec.i32 = bitcast <2 x i16> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
diff --git a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
index 9b03a72fd826d..a74db456ab6be 100644
--- a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
@@ -77,7 +77,7 @@ define amdgpu_kernel void @fadd_v2_v_v_splat(ptr addrspace(1) %a) {
%gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %a, i32 %id
%load = load <2 x float>, ptr addrspace(1) %gep, align 8
%fid = bitcast i32 %id to float
- %tmp1 = insertelement <2 x float> undef, float %fid, i64 0
+ %tmp1 = insertelement <2 x float> poison, float %fid, i64 0
%k = insertelement <2 x float> %tmp1, float %fid, i64 1
%add = fadd <2 x float> %load, %k
store <2 x float> %add, ptr addrspace(1) %gep, align 8
@@ -152,7 +152,7 @@ define amdgpu_kernel void @fadd_v2_v_fneg(ptr addrspace(1) %a, float %x) {
%gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %a, i32 %id
%load = load <2 x float>, ptr addrspace(1) %gep, align 8
%fneg = fsub float -0.0, %x
- %tmp1 = insertelement <2 x float> undef, float %fneg, i64 0
+ %tmp1 = insertelement <2 x float> poison, float %fneg, i64 0
%k = insertelement <2 x float> %tmp1, float %fneg, i64 1
%add = fadd <2 x float> %load, %k
store <2 x float> %add, ptr addrspace(1) %gep, align 8
@@ -169,7 +169,7 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo(ptr addrspace(1) %a, float %x) {
%gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %a, i32 %id
%load = load <2 x float>, ptr addrspace(1) %gep, align 8
%fneg = fsub float -0.0, %x
- %tmp1 = insertelement <2 x float> undef, float %fneg, i64 0
+ %tmp1 = insertelement <2 x float> poison, float %fneg, i64 0
%k = insertelement <2 x float> %tmp1, float %x, i64 1
%add = fadd <2 x float> %load, %k
store <2 x float> %add, ptr addrspace(1) %gep, align 8
@@ -186,7 +186,7 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi(ptr addrspace(1) %a, float %x) {
%gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %a, i32 %id
%load = load <2 x float>, ptr addrspace(1) %gep, align 8
%fneg = fsub float -0.0, %x
- %tmp1 = insertelement <2 x float> undef, float %x, i64 0
+ %tmp1 = insertelement <2 x float> poison, float %x, i64 0
%k = insertelement <2 x float> %tmp1, float %fneg, i64 1
%add = fadd <2 x float> %load, %k
store <2 x float> %add, ptr addrspace(1) %gep, align 8
@@ -203,7 +203,7 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo2(ptr addrspace(1) %a, float %x, flo
%gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %a, i32 %id
%load = load <2 x float>, ptr addrspace(1) %gep, align 8
%fneg = fsub float -0.0, %x
- %tmp1 = insertelement <2 x float> undef, float %fneg, i64 0
+ %tmp1 = insertelement <2 x float> poison, float %fneg, i64 0
%k = insertelement <2 x float> %tmp1, float %y, i64 1
%add = fadd <2 x float> %load, %k
store <2 x float> %add, ptr addrspace(1) %gep, align 8
@@ -220,7 +220,7 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi2(ptr addrspace(1) %a, float %x, flo
%gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %a, i32 %id
%load = load <2 x float>, ptr addrspace(1) %gep, align 8
%fneg = fsub float -0.0, %x
- %tmp1 = insertelement <2 x float> undef, float %y, i64 0
+ %tmp1 = insertelement <2 x float> poison, float %y, i64 0
%k = insertelement <2 x float> %tmp1, float %fneg, i64 1
%add = fadd <2 x float> %load, %k
store <2 x float> %add, ptr addrspace(1) %gep, align 8
@@ -298,7 +298,7 @@ define amdgpu_kernel void @fmul_v2_v_v_splat(ptr addrspace(1) %a) {
%gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %a, i32 %id
%load = load <2 x float>, ptr addrspace(1) %gep, align 8
%fid = bitcast i32 %id to float
- %tmp1 = insertelement <2 x float> undef, float %fid, i64 0
+ %tmp1 = insertelement <2 x float> poison, float %fid, i64 0
%k = insertelement <2 x float> %tmp1, float %fid, i64 1
%mul = fmul <2 x float> %load, %k
store <2 x float> %mul, ptr addrspace(1) %gep, align 8
@@ -342,7 +342,7 @@ define amdgpu_kernel void @fmul_v2_v_fneg(ptr addrspace(1) %a, float %x) {
%gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %a, i32 %id
%load = load <2 x float>, ptr addrspace(1) %gep, align 8
%fneg = fsub float -0.0, %x
- %tmp1 = insertelement <2 x float> undef, float %fneg, i64 0
+ %tmp1 = insertelement <2 x float> poison, float %fneg, i64 0
%k = insertelement <2 x float> %tmp1, float %fneg, i64 1
%mul = fmul <2 x float> %load, %k
store <2 x float> %mul, ptr addrspace(1) %gep, align 8
@@ -422,7 +422,7 @@ define amdgpu_kernel void @fma_v2_v_v_splat(ptr addrspace(1) %a) {
%gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %a, i32 %id
%load = load <2 x float>, ptr addrspace(1) %gep, align 8
%fid = bitcast i32 %id to float
- %tmp1 = insertelement <2 x float> undef, float %fid, i64 0
+ %tmp1 = insertelement <2 x float> poison, float %fid, i64 0
%k = insertelement <2 x float> %tmp1, float %fid, i64 1
%fma = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %load, <2 x float> %k, <2 x float> %k)
store <2 x float> %fma, ptr addrspace(1) %gep, align 8
@@ -468,7 +468,7 @@ define amdgpu_kernel void @fma_v2_v_fneg(ptr addrspace(1) %a, float %x) {
%gep = getelementptr inbounds <2 x float>, ptr addrspace(1) %a, i32 %id
%load = load <2 x float>, ptr addrspace(1) %gep, align 8
%fneg = fsub float -0.0, %x
- %tmp1 = insertelement <2 x float> undef, float %fneg, i64 0
+ %tmp1 = insertelement <2 x float> poison, float %fneg, i64 0
%k = insertelement <2 x float> %tmp1, float %fneg, i64 1
%fma = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %load, <2 x float> %k, <2 x float> %k)
store <2 x float> %fma, ptr addrspace(1) %gep, align 8
@@ -485,7 +485,7 @@ bb:
%scalar0 = load volatile float, ptr addrspace(3) %arg2, align 4
%neg.scalar0 = fsub float -0.0, %scalar0
- %neg.scalar0.vec = insertelement <2 x float> undef, float %neg.scalar0, i32 0
+ %neg.scalar0.vec = insertelement <2 x float> poison, float %neg.scalar0, i32 0
%neg.scalar0.broadcast = shufflevector <2 x float> %neg.scalar0.vec, <2 x float> undef, <2 x i32> zeroinitializer
%result = fadd <2 x float> %vec0, %neg.scalar0.broadcast
@@ -508,7 +508,7 @@ bb:
%scalar0 = load volatile float, ptr addrspace(3) %arg2, align 4
%scalar1 = load volatile float, ptr addrspace(3) %arg2.gep, align 4
- %vec.ins0 = insertelement <2 x float> undef, float %scalar0, i32 0
+ %vec.ins0 = insertelement <2 x float> poison, float %scalar0, i32 0
%vec2 = insertelement <2 x float> %vec.ins0, float %scalar1, i32 1
%neg.vec2 = fsub <2 x float> <float -0.0, float -0.0>, %vec2
diff --git a/llvm/test/CodeGen/AMDGPU/packed-op-sel.ll b/llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
index d6fc52bdb9322..5514cd3e0b367 100644
--- a/llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed-op-sel.ll
@@ -23,7 +23,7 @@ bb:
%vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4
%scalar0 = load volatile half, ptr addrspace(3) %arg2, align 2
- %scalar0.vec = insertelement <2 x half> undef, half %scalar0, i32 0
+ %scalar0.vec = insertelement <2 x half> poison, half %scalar0, i32 0
%scalar0.broadcast = shufflevector <2 x half> %scalar0.vec, <2 x half> undef, <2 x i32> zeroinitializer
%result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %scalar0.broadcast)
@@ -54,7 +54,7 @@ bb:
%vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4
%scalar0 = load volatile half, ptr addrspace(3) %arg2, align 2
- %scalar0.vec = insertelement <2 x half> undef, half %scalar0, i32 0
+ %scalar0.vec = insertelement <2 x half> poison, half %scalar0, i32 0
%scalar0.broadcast = shufflevector <2 x half> %scalar0.vec, <2 x half> undef, <2 x i32> zeroinitializer
%neg.scalar0.broadcast = fsub <2 x half> <half -0.0, half -0.0>, %scalar0.broadcast
@@ -87,7 +87,7 @@ bb:
%scalar0 = load volatile half, ptr addrspace(3) %arg2, align 2
%neg.scalar0 = fsub half -0.0, %scalar0
- %neg.scalar0.vec = insertelement <2 x half> undef, half %neg.scalar0, i32 0
+ %neg.scalar0.vec = insertelement <2 x half> poison, half %neg.scalar0, i32 0
%neg.scalar0.broadcast = shufflevector <2 x half> %neg.scalar0.vec, <2 x half> undef, <2 x i32> zeroinitializer
%result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.scalar0.broadcast)
@@ -119,7 +119,7 @@ bb:
%scalar0 = load volatile half, ptr addrspace(3) %arg2, align 2
%neg.scalar0 = fsub half -0.0, %scalar0
- %neg.scalar0.vec = insertelement <2 x half> undef, half %neg.scalar0, i32 0
+ %neg.scalar0.vec = insertelement <2 x half> poison, half %neg.scalar0, i32 0
%neg.scalar0.broadcast = shufflevector <2 x half> %neg.scalar0.vec, <2 x half> undef, <2 x i32> zeroinitializer
%neg.neg.scalar0.broadcast = fsub <2 x half> <half -0.0, half -0.0>, %neg.scalar0.broadcast
@@ -152,7 +152,7 @@ bb:
%scalar0 = load volatile half, ptr addrspace(3) %arg2, align 2
%neg.scalar0 = fsub half -0.0, %scalar0
- %neg.scalar0.vec = insertelement <2 x half> undef, half %neg.scalar0, i32 0
+ %neg.scalar0.vec = insertelement <2 x half> poison, half %neg.scalar0, i32 0
%neg.scalar0.scalar0 = insertelement <2 x half> %neg.scalar0.vec, half %scalar0, i32 1
%result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.scalar0.scalar0)
store <2 x half> %result, ptr addrspace(1) %out, align 4
@@ -183,7 +183,7 @@ bb:
%scalar0 = load volatile half, ptr addrspace(3) %arg2, align 2
%neg.scalar0 = fsub half -0.0, %scalar0
- %neg.scalar0.vec = insertelement <2 x half> undef, half %scalar0, i32 0
+ %neg.scalar0.vec = insertelement <2 x half> poison, half %scalar0, i32 0
%scalar0.neg.scalar0 = insertelement <2 x half> %neg.scalar0.vec, half %neg.scalar0, i32 1
%result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %scalar0.neg.scalar0)
store <2 x half> %result, ptr addrspace(1) %out, align 4
@@ -211,7 +211,7 @@ bb:
%neg.scalar0 = fsub half -0.0, %scalar0
%neg.scalar0.bc = bitcast half %neg.scalar0 to i16
- %neg.scalar0.vec = insertelement <2 x i16> undef, i16 %neg.scalar0.bc, i32 0
+ %neg.scalar0.vec = insertelement <2 x i16> poison, i16 %neg.scalar0.bc, i32 0
%neg.scalar0.broadcast = shufflevector <2 x i16> %neg.scalar0.vec, <2 x i16> undef, <2 x i32> zeroinitializer
%result = add <2 x i16> %vec0, %neg.scalar0.broadcast
@@ -250,7 +250,7 @@ bb:
%scalar1 = load volatile half, ptr addrspace(3) %arg2.gep, align 2
%neg.scalar1 = fsub half -0.0, %scalar1
- %vec.ins0 = insertelement <2 x half> undef, half %scalar0, i32 0
+ %vec.ins0 = insertelement <2 x half> poison, half %scalar0, i32 0
%vec2 = insertelement <2 x half> %vec.ins0, half %neg.scalar1, i32 1
%result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %vec2)
store <2 x half> %result, ptr addrspace(1) %out, align 4
@@ -285,7 +285,7 @@ bb:
%scalar0 = load volatile half, ptr addrspace(3) %arg2, align 2
%scalar1 = load volatile half, ptr addrspace(3) %arg2.gep, align 2
- %vec.ins0 = insertelement <2 x half> undef, half %scalar0, i32 0
+ %vec.ins0 = insertelement <2 x half> poison, half %scalar0, i32 0
%vec2 = insertelement <2 x half> %vec.ins0, half %scalar1, i32 1
%neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2
@@ -710,7 +710,7 @@ bb:
%hi = lshr i64 %i64, 16
%elt1 = trunc i64 %hi to i16
- %ins0 = insertelement <2 x i16> undef, i16 %elt1, i32 0
+ %ins0 = insertelement <2 x i16> poison, i16 %elt1, i32 0
%ins1 = insertelement <2 x i16> %ins0, i16 %elt0, i32 1
%result = add <2 x i16> %vec0, %ins1
store <2 x i16> %result, ptr addrspace(1) %out, align 4
@@ -791,7 +791,7 @@ bb:
%shl = shl i16 %scalar0, 1
%shl.bc = bitcast i16 %shl to half
- %insert0 = insertelement <2 x half> undef, half %shl.bc, i32 0
+ %insert0 = insertelement <2 x half> poison, half %shl.bc, i32 0
%fadd = fadd <2 x half> %vec2, <half 2.0, half 2.0>
%insert1 = shufflevector <2 x half> %fadd, <2 x half> %insert0, <2 x i32> <i32 1, i32 0>
diff --git a/llvm/test/CodeGen/AMDGPU/predicate-dp4.ll b/llvm/test/CodeGen/AMDGPU/predicate-dp4.ll
index 9e2778bb3e71a..e807765c2604b 100644
--- a/llvm/test/CodeGen/AMDGPU/predicate-dp4.ll
+++ b/llvm/test/CodeGen/AMDGPU/predicate-dp4.ll
@@ -16,7 +16,7 @@ IF: ; preds = %main_body
ENDIF: ; preds = %IF, %main_body
%5 = phi float [%4, %IF], [0.000000e+00, %main_body]
- %6 = insertelement <4 x float> undef, float %5, i32 0
+ %6 = insertelement <4 x float> poison, float %5, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %6, i32 0, i32 0)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll b/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
index e3f258717aad9..5b9b0feea9900 100644
--- a/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
+++ b/llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
@@ -6,7 +6,7 @@
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_1_arg(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18) local_unnamed_addr #0 {
.entry:
%i1 = extractelement <2 x float> %arg3, i32 1
- %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+ %ret1 = insertelement <4 x float> poison, float %i1, i32 0
%ret2 = insertvalue { <4 x float> } poison, <4 x float> %ret1, 0
ret { <4 x float> } %ret2
}
@@ -18,7 +18,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_3_arg(i32 inreg %arg, i32
%i1 = extractelement <2 x float> %arg3, i32 1
%i2 = extractelement <2 x float> %arg4, i32 0
%i3 = extractelement <2 x float> %arg5, i32 1
- %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+ %ret1 = insertelement <4 x float> poison, float %i1, i32 0
%ret1.1 = insertelement <4 x float> %ret1, float %i2, i32 1
%ret1.2 = insertelement <4 x float> %ret1.1, float %i3, i32 2
%ret2 = insertvalue { <4 x float> } poison, <4 x float> %ret1.2, 0
@@ -31,7 +31,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_2_arg_gap(i32 inreg %arg,
.entry:
%i1 = extractelement <2 x float> %arg3, i32 1
%i3 = extractelement <2 x float> %arg5, i32 1
- %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+ %ret1 = insertelement <4 x float> poison, float %i1, i32 0
%ret1.2 = insertelement <4 x float> %ret1, float %i3, i32 1
%ret2 = insertvalue { <4 x float> } poison, <4 x float> %ret1.2, 0
ret { <4 x float> } %ret2
@@ -45,7 +45,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_2_arg_no_pack(i32 inreg %
.entry:
%i1 = extractelement <2 x float> %arg3, i32 1
%i3 = extractelement <2 x float> %arg5, i32 1
- %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+ %ret1 = insertelement <4 x float> poison, float %i1, i32 0
%ret1.2 = insertelement <4 x float> %ret1, float %i3, i32 1
%ret2 = insertvalue { <4 x float> } poison, <4 x float> %ret1.2, 0
ret { <4 x float> } %ret2
@@ -63,17 +63,17 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%i6 = extractelement <2 x float> %arg8, i32 0
%i7 = extractelement <2 x float> %arg9, i32 1
- %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+ %ret1 = insertelement <4 x float> poison, float %i1, i32 0
%ret1.1 = insertelement <4 x float> %ret1, float %i2, i32 1
%ret1.2 = insertelement <4 x float> %ret1.1, float %i3, i32 2
%ret1.3 = insertelement <4 x float> %ret1.2, float %i4, i32 3
- %ret2 = insertelement <4 x float> undef, float %i5, i32 0
+ %ret2 = insertelement <4 x float> poison, float %i5, i32 0
%ret2.1 = insertelement <4 x float> %ret2, float %i6, i32 1
%ret2.2 = insertelement <4 x float> %ret2.1, float %i7, i32 2
%ret2.3 = insertelement <4 x float> %ret2.2, float %arg10, i32 3
- %ret3 = insertelement <4 x float> undef, float %arg11, i32 0
+ %ret3 = insertelement <4 x float> poison, float %arg11, i32 0
%ret3.1 = insertelement <4 x float> %ret3, float %arg12, i32 1
%ret3.2 = insertelement <4 x float> %ret3.1, float %arg13, i32 2
%ret3.3 = insertelement <4 x float> %ret3.2, float %arg14, i32 3
@@ -83,7 +83,7 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%arg17.f = bitcast i32 %arg17 to float
%arg18.f = bitcast i32 %arg18 to float
- %ret4 = insertelement <4 x float> undef, float %arg15.f, i32 0
+ %ret4 = insertelement <4 x float> poison, float %arg15.f, i32 0
%ret4.1 = insertelement <4 x float> %ret4, float %arg16.f, i32 1
%ret4.2 = insertelement <4 x float> %ret4.1, float %arg17.f, i32 2
%ret4.3 = insertelement <4 x float> %ret4.2, float %arg18.f, i32 3
@@ -109,17 +109,17 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%i6 = extractelement <2 x float> %arg8, i32 0
%i7 = extractelement <2 x float> %arg9, i32 1
- %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+ %ret1 = insertelement <4 x float> poison, float %i1, i32 0
%ret1.1 = insertelement <4 x float> %ret1, float %i2, i32 1
%ret1.2 = insertelement <4 x float> %ret1.1, float %i3, i32 2
%ret1.3 = insertelement <4 x float> %ret1.2, float %i4, i32 3
- %ret2 = insertelement <4 x float> undef, float %i5, i32 0
+ %ret2 = insertelement <4 x float> poison, float %i5, i32 0
%ret2.1 = insertelement <4 x float> %ret2, float %i6, i32 1
%ret2.2 = insertelement <4 x float> %ret2.1, float %i7, i32 2
%ret2.3 = insertelement <4 x float> %ret2.2, float %arg10, i32 3
- %ret3 = insertelement <4 x float> undef, float %arg11, i32 0
+ %ret3 = insertelement <4 x float> poison, float %arg11, i32 0
%ret3.1 = insertelement <4 x float> %ret3, float %arg12, i32 1
%ret3.2 = insertelement <4 x float> %ret3.1, float %arg13, i32 2
%ret3.3 = insertelement <4 x float> %ret3.2, float %arg14, i32 3
@@ -129,7 +129,7 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%arg17.f = bitcast i32 %arg17 to float
%arg18.f = bitcast i32 %arg18 to float
- %ret4 = insertelement <4 x float> undef, float %arg15.f, i32 0
+ %ret4 = insertelement <4 x float> poison, float %arg15.f, i32 0
%ret4.1 = insertelement <4 x float> %ret4, float %arg16.f, i32 1
%ret4.2 = insertelement <4 x float> %ret4.1, float %arg17.f, i32 2
%ret4.3 = insertelement <4 x float> %ret4.2, float %arg18.f, i32 3
@@ -155,17 +155,17 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%i6 = extractelement <2 x float> %arg8, i32 0
%i7 = extractelement <2 x float> %arg9, i32 1
- %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+ %ret1 = insertelement <4 x float> poison, float %i1, i32 0
%ret1.1 = insertelement <4 x float> %ret1, float %i2, i32 1
%ret1.2 = insertelement <4 x float> %ret1.1, float %i3, i32 2
%ret1.3 = insertelement <4 x float> %ret1.2, float %i4, i32 3
- %ret2 = insertelement <4 x float> undef, float %i5, i32 0
+ %ret2 = insertelement <4 x float> poison, float %i5, i32 0
%ret2.1 = insertelement <4 x float> %ret2, float %i6, i32 1
%ret2.2 = insertelement <4 x float> %ret2.1, float %i7, i32 2
%ret2.3 = insertelement <4 x float> %ret2.2, float %arg10, i32 3
- %ret3 = insertelement <4 x float> undef, float %arg11, i32 0
+ %ret3 = insertelement <4 x float> poison, float %arg11, i32 0
%ret3.1 = insertelement <4 x float> %ret3, float %arg12, i32 1
%ret3.2 = insertelement <4 x float> %ret3.1, float %arg13, i32 2
%ret3.3 = insertelement <4 x float> %ret3.2, float %arg14, i32 3
@@ -178,7 +178,7 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%arg15_16.f = fadd float %arg15.f, %arg16.f
%arg17_18.f = fadd float %arg17.f, %arg18.f
- %ret4 = insertelement <4 x float> undef, float %extra_arg1, i32 0
+ %ret4 = insertelement <4 x float> poison, float %extra_arg1, i32 0
%ret4.1 = insertelement <4 x float> %ret4, float %extra_arg2, i32 1
%ret4.2 = insertelement <4 x float> %ret4.1, float %arg15_16.f, i32 2
%ret4.3 = insertelement <4 x float> %ret4.2, float %arg17_18.f, i32 3
@@ -212,7 +212,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_ia0(i32 inreg
; CHECK: NumVgprs: 4
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_used(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
.entry:
- %ret4.1 = insertelement <4 x float> undef, float %extra_arg1, i32 0
+ %ret4.1 = insertelement <4 x float> poison, float %extra_arg1, i32 0
%ret4.2 = insertelement <4 x float> %ret4.1, float %extra_arg2, i32 1
%ret.res = insertvalue { <4 x float> } poison, <4 x float> %ret4.2, 0
@@ -224,7 +224,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_used(i32
; CHECK: NumVgprs: 5
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_part_unused_extra_used(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
.entry:
- %ret4.1 = insertelement <4 x float> undef, float %arg14, i32 0
+ %ret4.1 = insertelement <4 x float> poison, float %arg14, i32 0
%ret4.2 = insertelement <4 x float> %ret4.1, float %extra_arg1, i32 1
%ret4.3 = insertelement <4 x float> %ret4.2, float %extra_arg2, i32 2
@@ -237,7 +237,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_part_unused_extra_used(i3
; CHECK: NumVgprs: 7
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_part_unused_extra_unused(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #0 {
.entry:
- %ret4.1 = insertelement <4 x float> undef, float %arg12, i32 0
+ %ret4.1 = insertelement <4 x float> poison, float %arg12, i32 0
%ret4.2 = insertelement <4 x float> %ret4.1, float %arg13, i32 1
%ret4.3 = insertelement <4 x float> %ret4.2, float %arg14, i32 2
@@ -259,7 +259,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_unused(i
; CHECK: NumVgprs: 26
define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_used_no_packing(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x float> %arg3, <2 x float> %arg4, <2 x float> %arg5, <3 x float> %arg6, <2 x float> %arg7, <2 x float> %arg8, <2 x float> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, i32 %arg15, i32 %arg16, i32 %arg17, i32 %arg18, float %extra_arg1, float %extra_arg2) local_unnamed_addr #2 {
.entry:
- %ret4.1 = insertelement <4 x float> undef, float %extra_arg1, i32 0
+ %ret4.1 = insertelement <4 x float> poison, float %extra_arg1, i32 0
%ret4.2 = insertelement <4 x float> %ret4.1, float %extra_arg2, i32 1
%ret.res = insertvalue { <4 x float> } poison, <4 x float> %ret4.2, 0
@@ -287,17 +287,17 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%i6 = extractelement <2 x float> %arg8, i32 0
%i7 = extractelement <2 x float> %arg9, i32 1
- %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+ %ret1 = insertelement <4 x float> poison, float %i1, i32 0
%ret1.1 = insertelement <4 x float> %ret1, float %i2, i32 1
%ret1.2 = insertelement <4 x float> %ret1.1, float %i3, i32 2
%ret1.3 = insertelement <4 x float> %ret1.2, float %i4, i32 3
- %ret2 = insertelement <4 x float> undef, float %i5, i32 0
+ %ret2 = insertelement <4 x float> poison, float %i5, i32 0
%ret2.1 = insertelement <4 x float> %ret2, float %i6, i32 1
%ret2.2 = insertelement <4 x float> %ret2.1, float %i7, i32 2
%ret2.3 = insertelement <4 x float> %ret2.2, float %arg10, i32 3
- %ret3 = insertelement <4 x float> undef, float %arg11, i32 0
+ %ret3 = insertelement <4 x float> poison, float %arg11, i32 0
%ret3.1 = insertelement <4 x float> %ret3, float %arg12, i32 1
%ret3.2 = insertelement <4 x float> %ret3.1, float %arg13, i32 2
%ret3.3 = insertelement <4 x float> %ret3.2, float %arg14, i32 3
@@ -305,7 +305,7 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%arg15.f = bitcast i32 %arg15 to float
%arg16.f = bitcast i32 %arg16 to float
- %ret4 = insertelement <4 x float> undef, float %extra_arg1, i32 0
+ %ret4 = insertelement <4 x float> poison, float %extra_arg1, i32 0
%ret4.1 = insertelement <4 x float> %ret4, float %extra_arg2, i32 1
%ret4.2 = insertelement <4 x float> %ret4.1, float %arg15.f, i32 2
%ret4.3 = insertelement <4 x float> %ret4.2, float %arg16.f, i32 3
@@ -331,22 +331,22 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%i6 = extractelement <2 x float> %arg8, i32 0
%i7 = extractelement <2 x float> %arg9, i32 1
- %ret1 = insertelement <4 x float> undef, float %i1, i32 0
+ %ret1 = insertelement <4 x float> poison, float %i1, i32 0
%ret1.1 = insertelement <4 x float> %ret1, float %i2, i32 1
%ret1.2 = insertelement <4 x float> %ret1.1, float %i3, i32 2
%ret1.3 = insertelement <4 x float> %ret1.2, float %i4, i32 3
- %ret2 = insertelement <4 x float> undef, float %i5, i32 0
+ %ret2 = insertelement <4 x float> poison, float %i5, i32 0
%ret2.1 = insertelement <4 x float> %ret2, float %i6, i32 1
%ret2.2 = insertelement <4 x float> %ret2.1, float %i7, i32 2
%ret2.3 = insertelement <4 x float> %ret2.2, float %arg10, i32 3
- %ret3 = insertelement <4 x float> undef, float %arg11, i32 0
+ %ret3 = insertelement <4 x float> poison, float %arg11, i32 0
%ret3.1 = insertelement <4 x float> %ret3, float %arg12, i32 1
%ret3.2 = insertelement <4 x float> %ret3.1, float %arg13, i32 2
%ret3.3 = insertelement <4 x float> %ret3.2, float %arg14, i32 3
- %ret4 = insertelement <4 x float> undef, float %extra_arg1, i32 0
+ %ret4 = insertelement <4 x float> poison, float %extra_arg1, i32 0
%ret4.1 = insertelement <4 x float> %ret4, float %extra_arg2, i32 1
%ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } poison, <4 x float> %ret1.3, 0
diff --git a/llvm/test/CodeGen/AMDGPU/pv-packing.ll b/llvm/test/CodeGen/AMDGPU/pv-packing.ll
index 1d6c751278c68..a83b28d297905 100644
--- a/llvm/test/CodeGen/AMDGPU/pv-packing.ll
+++ b/llvm/test/CodeGen/AMDGPU/pv-packing.ll
@@ -42,12 +42,12 @@ main_body:
%17 = fadd float %16, %8
%18 = fmul float %11, %11
%19 = fadd float %18, %0
- %20 = insertelement <4 x float> undef, float %13, i32 0
+ %20 = insertelement <4 x float> poison, float %13, i32 0
%21 = insertelement <4 x float> %20, float %15, i32 1
%22 = insertelement <4 x float> %21, float %17, i32 2
%23 = insertelement <4 x float> %22, float %19, i32 3
%24 = call float @llvm.r600.dot4(<4 x float> %23, <4 x float> %10)
- %25 = insertelement <4 x float> undef, float %24, i32 0
+ %25 = insertelement <4 x float> poison, float %24, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %25, i32 0, i32 2)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/pv.ll b/llvm/test/CodeGen/AMDGPU/pv.ll
index 856457aa58cbf..96db6ec436a2d 100644
--- a/llvm/test/CodeGen/AMDGPU/pv.ll
+++ b/llvm/test/CodeGen/AMDGPU/pv.ll
@@ -92,11 +92,11 @@ main_body:
%tmp97 = extractelement <4 x float> %tmp96, i32 3
%tmp98 = fmul float %tmp15, %tmp97
%tmp99 = fadd float %tmp98, %tmp83
- %tmp100 = insertelement <4 x float> undef, float %tmp16, i32 0
+ %tmp100 = insertelement <4 x float> poison, float %tmp16, i32 0
%tmp101 = insertelement <4 x float> %tmp100, float %tmp17, i32 1
%tmp102 = insertelement <4 x float> %tmp101, float %tmp18, i32 2
%tmp103 = insertelement <4 x float> %tmp102, float 0.000000e+00, i32 3
- %tmp104 = insertelement <4 x float> undef, float %tmp16, i32 0
+ %tmp104 = insertelement <4 x float> poison, float %tmp16, i32 0
%tmp105 = insertelement <4 x float> %tmp104, float %tmp17, i32 1
%tmp106 = insertelement <4 x float> %tmp105, float %tmp18, i32 2
%tmp107 = insertelement <4 x float> %tmp106, float 0.000000e+00, i32 3
@@ -132,11 +132,11 @@ main_body:
%tmp129 = extractelement <4 x float> %tmp128, i32 1
%tmp130 = load <4 x float>, ptr addrspace(8) getelementptr ([1024 x <4 x float>], ptr addrspace(8) null, i64 0, i32 5)
%tmp131 = extractelement <4 x float> %tmp130, i32 2
- %tmp132 = insertelement <4 x float> undef, float %tmp111, i32 0
+ %tmp132 = insertelement <4 x float> poison, float %tmp111, i32 0
%tmp133 = insertelement <4 x float> %tmp132, float %tmp112, i32 1
%tmp134 = insertelement <4 x float> %tmp133, float %tmp113, i32 2
%tmp135 = insertelement <4 x float> %tmp134, float 0.000000e+00, i32 3
- %tmp136 = insertelement <4 x float> undef, float %tmp127, i32 0
+ %tmp136 = insertelement <4 x float> poison, float %tmp127, i32 0
%tmp137 = insertelement <4 x float> %tmp136, float %tmp129, i32 1
%tmp138 = insertelement <4 x float> %tmp137, float %tmp131, i32 2
%tmp139 = insertelement <4 x float> %tmp138, float 0.000000e+00, i32 3
@@ -147,11 +147,11 @@ main_body:
%tmp144 = extractelement <4 x float> %tmp143, i32 1
%tmp145 = load <4 x float>, ptr addrspace(8) getelementptr ([1024 x <4 x float>], ptr addrspace(8) null, i64 0, i32 7)
%tmp146 = extractelement <4 x float> %tmp145, i32 2
- %tmp147 = insertelement <4 x float> undef, float %tmp111, i32 0
+ %tmp147 = insertelement <4 x float> poison, float %tmp111, i32 0
%tmp148 = insertelement <4 x float> %tmp147, float %tmp112, i32 1
%tmp149 = insertelement <4 x float> %tmp148, float %tmp113, i32 2
%tmp150 = insertelement <4 x float> %tmp149, float 0.000000e+00, i32 3
- %tmp151 = insertelement <4 x float> undef, float %tmp142, i32 0
+ %tmp151 = insertelement <4 x float> poison, float %tmp142, i32 0
%tmp152 = insertelement <4 x float> %tmp151, float %tmp144, i32 1
%tmp153 = insertelement <4 x float> %tmp152, float %tmp146, i32 2
%tmp154 = insertelement <4 x float> %tmp153, float 0.000000e+00, i32 3
@@ -211,12 +211,12 @@ main_body:
%clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
%max.0.i1 = call float @llvm.maxnum.f32(float %tmp204, float 0.000000e+00)
%clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
- %tmp205 = insertelement <4 x float> undef, float %tmp87, i32 0
+ %tmp205 = insertelement <4 x float> poison, float %tmp87, i32 0
%tmp206 = insertelement <4 x float> %tmp205, float %tmp91, i32 1
%tmp207 = insertelement <4 x float> %tmp206, float %tmp95, i32 2
%tmp208 = insertelement <4 x float> %tmp207, float %tmp99, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %tmp208, i32 60, i32 1)
- %tmp209 = insertelement <4 x float> undef, float %clamp.i6, i32 0
+ %tmp209 = insertelement <4 x float> poison, float %clamp.i6, i32 0
%tmp210 = insertelement <4 x float> %tmp209, float %clamp.i4, i32 1
%tmp211 = insertelement <4 x float> %tmp210, float %clamp.i2, i32 2
%tmp212 = insertelement <4 x float> %tmp211, float %clamp.i8, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/r600-encoding.ll b/llvm/test/CodeGen/AMDGPU/r600-encoding.ll
index 2580c58f56057..bd20af36c37c1 100644
--- a/llvm/test/CodeGen/AMDGPU/r600-encoding.ll
+++ b/llvm/test/CodeGen/AMDGPU/r600-encoding.ll
@@ -15,7 +15,7 @@ entry:
%r0 = extractelement <4 x float> %reg0, i32 0
%r1 = extractelement <4 x float> %reg0, i32 1
%r2 = fmul float %r0, %r1
- %vec = insertelement <4 x float> undef, float %r2, i32 0
+ %vec = insertelement <4 x float> poison, float %r2, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll b/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll
index 21a7050c2c320..4740a21ed1313 100644
--- a/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll
+++ b/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll
@@ -125,42 +125,42 @@ main_body:
%79 = extractelement <4 x float> %78, i32 1
%80 = load <4 x float>, ptr addrspace(8) getelementptr ([1024 x <4 x float>], ptr addrspace(8) null, i64 0, i32 3)
%81 = extractelement <4 x float> %80, i32 2
- %82 = insertelement <4 x float> undef, float %51, i32 0
+ %82 = insertelement <4 x float> poison, float %51, i32 0
%83 = insertelement <4 x float> %82, float %55, i32 1
%84 = insertelement <4 x float> %83, float %59, i32 2
%85 = insertelement <4 x float> %84, float %63, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %85, i32 60, i32 1)
- %86 = insertelement <4 x float> undef, float 0.000000e+00, i32 0
+ %86 = insertelement <4 x float> poison, float 0.000000e+00, i32 0
%87 = insertelement <4 x float> %86, float 0.000000e+00, i32 1
%88 = insertelement <4 x float> %87, float 0.000000e+00, i32 2
%89 = insertelement <4 x float> %88, float 0.000000e+00, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %89, i32 0, i32 2)
- %90 = insertelement <4 x float> undef, float 0.000000e+00, i32 0
+ %90 = insertelement <4 x float> poison, float 0.000000e+00, i32 0
%91 = insertelement <4 x float> %90, float 0.000000e+00, i32 1
%92 = insertelement <4 x float> %91, float 0.000000e+00, i32 2
%93 = insertelement <4 x float> %92, float 0.000000e+00, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %93, i32 1, i32 2)
- %94 = insertelement <4 x float> undef, float 0.000000e+00, i32 0
+ %94 = insertelement <4 x float> poison, float 0.000000e+00, i32 0
%95 = insertelement <4 x float> %94, float %65, i32 1
%96 = insertelement <4 x float> %95, float %67, i32 2
%97 = insertelement <4 x float> %96, float %69, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %97, i32 2, i32 2)
- %98 = insertelement <4 x float> undef, float %77, i32 0
+ %98 = insertelement <4 x float> poison, float %77, i32 0
%99 = insertelement <4 x float> %98, float %79, i32 1
%100 = insertelement <4 x float> %99, float %81, i32 2
%101 = insertelement <4 x float> %100, float %71, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %101, i32 3, i32 2)
- %102 = insertelement <4 x float> undef, float %73, i32 0
+ %102 = insertelement <4 x float> poison, float %73, i32 0
%103 = insertelement <4 x float> %102, float %75, i32 1
%104 = insertelement <4 x float> %103, float 0.000000e+00, i32 2
%105 = insertelement <4 x float> %104, float 0.000000e+00, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %105, i32 4, i32 2)
- %106 = insertelement <4 x float> undef, float 0.000000e+00, i32 0
+ %106 = insertelement <4 x float> poison, float 0.000000e+00, i32 0
%107 = insertelement <4 x float> %106, float 0.000000e+00, i32 1
%108 = insertelement <4 x float> %107, float 0.000000e+00, i32 2
%109 = insertelement <4 x float> %108, float 0.000000e+00, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %109, i32 5, i32 2)
- %110 = insertelement <4 x float> undef, float 0.000000e+00, i32 0
+ %110 = insertelement <4 x float> poison, float 0.000000e+00, i32 0
%111 = insertelement <4 x float> %110, float 0.000000e+00, i32 1
%112 = insertelement <4 x float> %111, float 0.000000e+00, i32 2
%113 = insertelement <4 x float> %112, float 0.000000e+00, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll b/llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
index 54cc43ce36b9f..d815c18a289e1 100644
--- a/llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
@@ -6,7 +6,7 @@ main_body:
%tmp2 = extractelement <4 x float> %arg, i32 1
%tmp3 = extractelement <4 x float> %arg, i32 2
%tmp4 = extractelement <4 x float> %arg, i32 3
- %tmp5 = insertelement <4 x float> undef, float %tmp, i32 0
+ %tmp5 = insertelement <4 x float> poison, float %tmp, i32 0
%tmp6 = insertelement <4 x float> %tmp5, float %tmp2, i32 1
%tmp7 = insertelement <4 x float> %tmp6, float %tmp3, i32 2
%tmp8 = insertelement <4 x float> %tmp7, float %tmp4, i32 3
@@ -21,7 +21,7 @@ main_body:
%tmp17 = fadd float %tmp16, 1.500000e+00
%tmp18 = fmul float %tmp11, %tmp15
%tmp19 = fadd float %tmp18, 1.500000e+00
- %tmp20 = insertelement <4 x float> undef, float %tmp19, i32 0
+ %tmp20 = insertelement <4 x float> poison, float %tmp19, i32 0
%tmp21 = insertelement <4 x float> %tmp20, float %tmp17, i32 1
%tmp22 = insertelement <4 x float> %tmp21, float %tmp13, i32 2
%tmp23 = insertelement <4 x float> %tmp22, float %tmp4, i32 3
@@ -29,14 +29,14 @@ main_body:
%tmp25 = extractelement <4 x float> %tmp23, i32 1
%tmp26 = extractelement <4 x float> %tmp23, i32 2
%tmp27 = extractelement <4 x float> %tmp23, i32 3
- %tmp28 = insertelement <4 x float> undef, float %tmp24, i32 0
+ %tmp28 = insertelement <4 x float> poison, float %tmp24, i32 0
%tmp29 = insertelement <4 x float> %tmp28, float %tmp25, i32 1
%tmp30 = insertelement <4 x float> %tmp29, float %tmp26, i32 2
%tmp31 = insertelement <4 x float> %tmp30, float %tmp27, i32 3
%tmp32 = shufflevector <4 x float> %tmp31, <4 x float> %tmp31, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp33 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp32, i32 0, i32 0, i32 0, i32 16, i32 0, i32 1, i32 1, i32 1, i32 1)
%tmp34 = extractelement <4 x float> %tmp33, i32 0
- %tmp35 = insertelement <4 x float> undef, float %tmp34, i32 0
+ %tmp35 = insertelement <4 x float> poison, float %tmp34, i32 0
%tmp36 = insertelement <4 x float> %tmp35, float %tmp34, i32 1
%tmp37 = insertelement <4 x float> %tmp36, float %tmp34, i32 2
%tmp38 = insertelement <4 x float> %tmp37, float 1.000000e+00, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/r600cfg.ll b/llvm/test/CodeGen/AMDGPU/r600cfg.ll
index 663b13a913ee2..e5a30298703e4 100644
--- a/llvm/test/CodeGen/AMDGPU/r600cfg.ll
+++ b/llvm/test/CodeGen/AMDGPU/r600cfg.ll
@@ -28,27 +28,27 @@ LOOP: ; preds = %LOOP47, %main_body
br i1 %15, label %IF41, label %ENDIF40
IF41: ; preds = %LOOP
- %16 = insertelement <4 x float> undef, float %0, i32 0
+ %16 = insertelement <4 x float> poison, float %0, i32 0
%17 = insertelement <4 x float> %16, float %temp8.0, i32 1
%18 = insertelement <4 x float> %17, float %temp12.0, i32 2
%19 = insertelement <4 x float> %18, float 0.000000e+00, i32 3
call void @llvm.r600.store.stream.output(<4 x float> %19, i32 0, i32 0, i32 1)
- %20 = insertelement <4 x float> undef, float %0, i32 0
+ %20 = insertelement <4 x float> poison, float %0, i32 0
%21 = insertelement <4 x float> %20, float %temp8.0, i32 1
%22 = insertelement <4 x float> %21, float %temp12.0, i32 2
%23 = insertelement <4 x float> %22, float 0.000000e+00, i32 3
call void @llvm.r600.store.stream.output(<4 x float> %23, i32 0, i32 0, i32 2)
- %24 = insertelement <4 x float> undef, float %0, i32 0
+ %24 = insertelement <4 x float> poison, float %0, i32 0
%25 = insertelement <4 x float> %24, float %temp8.0, i32 1
%26 = insertelement <4 x float> %25, float %temp12.0, i32 2
%27 = insertelement <4 x float> %26, float 0.000000e+00, i32 3
call void @llvm.r600.store.stream.output(<4 x float> %27, i32 0, i32 0, i32 4)
- %28 = insertelement <4 x float> undef, float 0.000000e+00, i32 0
+ %28 = insertelement <4 x float> poison, float 0.000000e+00, i32 0
%29 = insertelement <4 x float> %28, float 0.000000e+00, i32 1
%30 = insertelement <4 x float> %29, float 0.000000e+00, i32 2
%31 = insertelement <4 x float> %30, float 0.000000e+00, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %31, i32 60, i32 1)
- %32 = insertelement <4 x float> undef, float %0, i32 0
+ %32 = insertelement <4 x float> poison, float %0, i32 0
%33 = insertelement <4 x float> %32, float %temp8.0, i32 1
%34 = insertelement <4 x float> %33, float %temp12.0, i32 2
%35 = insertelement <4 x float> %34, float 0.000000e+00, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll b/llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll
index 22fe358b3b6be..509b88250b4f1 100644
--- a/llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll
@@ -56,7 +56,7 @@ define amdgpu_kernel void @reassoc_v2i32(ptr addrspace(1) %arg, <2 x i32> %x, <2
bb:
%t1 = tail call i32 @llvm.amdgcn.workitem.id.x()
%t2 = tail call i32 @llvm.amdgcn.workitem.id.y()
- %v1 = insertelement <2 x i32> undef, i32 %t1, i32 0
+ %v1 = insertelement <2 x i32> poison, i32 %t1, i32 0
%v2 = insertelement <2 x i32> %v1, i32 %t2, i32 1
%add1 = add <2 x i32> %x, %v2
%add2 = add <2 x i32> %add1, %y
diff --git a/llvm/test/CodeGen/AMDGPU/rv7x0_count3.ll b/llvm/test/CodeGen/AMDGPU/rv7x0_count3.ll
index 30f32e1f3e336..cd7631c962944 100644
--- a/llvm/test/CodeGen/AMDGPU/rv7x0_count3.ll
+++ b/llvm/test/CodeGen/AMDGPU/rv7x0_count3.ll
@@ -7,7 +7,7 @@ bb:
%tmp1 = extractelement <4 x float> %reg1, i32 1
%tmp2 = extractelement <4 x float> %reg1, i32 2
%tmp3 = extractelement <4 x float> %reg1, i32 3
- %tmp4 = insertelement <4 x float> undef, float %tmp, i32 0
+ %tmp4 = insertelement <4 x float> poison, float %tmp, i32 0
%tmp5 = insertelement <4 x float> %tmp4, float %tmp1, i32 1
%tmp6 = insertelement <4 x float> %tmp5, float %tmp2, i32 2
%tmp7 = insertelement <4 x float> %tmp6, float %tmp3, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
index e14666cdac5c2..b744d3357b8ab 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
@@ -281,8 +281,8 @@ bb:
; }
; define amdgpu_kernel void @scalar_to_vector_test3(ptr addrspace(1) %out) nounwind {
-; %newvec0 = insertelement <2 x i64> undef, i64 12345, i32 0
-; %newvec1 = insertelement <2 x i64> %newvec0, i64 undef, i32 1
+; %newvec0 = insertelement <2 x i64> poison, i64 12345, i32 0
+; %newvec1 = insertelement <2 x i64> %newvec0, i64 poison, i32 1
; %bc = bitcast <2 x i64> %newvec1 to <4 x i32>
; %add = add <4 x i32> %bc, <i32 1, i32 2, i32 3, i32 4>
; store <4 x i32> %add, ptr addrspace(1) %out, align 16
@@ -290,7 +290,7 @@ bb:
; }
; define amdgpu_kernel void @scalar_to_vector_test4(ptr addrspace(1) %out) nounwind {
-; %newvec0 = insertelement <4 x i32> undef, i32 12345, i32 0
+; %newvec0 = insertelement <4 x i32> poison, i32 12345, i32 0
; %bc = bitcast <4 x i32> %newvec0 to <8 x i16>
; %add = add <8 x i16> %bc, <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>
; store <8 x i16> %add, ptr addrspace(1) %out, align 16
@@ -298,7 +298,7 @@ bb:
; }
; define amdgpu_kernel void @scalar_to_vector_test5(ptr addrspace(1) %out) nounwind {
-; %newvec0 = insertelement <2 x i32> undef, i32 12345, i32 0
+; %newvec0 = insertelement <2 x i32> poison, i32 12345, i32 0
; %bc = bitcast <2 x i32> %newvec0 to <4 x i16>
; %add = add <4 x i16> %bc, <i16 1, i16 2, i16 3, i16 4>
; store <4 x i16> %add, ptr addrspace(1) %out, align 16
@@ -327,7 +327,7 @@ define amdgpu_kernel void @scalar_to_vector_test6(ptr addrspace(1) %out, i8 zero
; GFX89-NEXT: v_mov_b32_e32 v0, s6
; GFX89-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX89-NEXT: s_endpgm
- %newvec0 = insertelement <4 x i8> undef, i8 %val, i32 0
+ %newvec0 = insertelement <4 x i8> poison, i8 %val, i32 0
%bc = bitcast <4 x i8> %newvec0 to <2 x half>
store <2 x half> %bc, ptr addrspace(1) %out
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll b/llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll
index ae779eb3410ff..63d75f3ad0b01 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll
+++ b/llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll
@@ -50,7 +50,7 @@ ENDIF: ; preds = %ELSE17, %ELSE, %IF
%clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
%max.0.i1 = call float @llvm.maxnum.f32(float %temp2.0, float 0.000000e+00)
%clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
- %tmp31 = insertelement <4 x float> undef, float %clamp.i, i32 0
+ %tmp31 = insertelement <4 x float> poison, float %clamp.i, i32 0
%tmp32 = insertelement <4 x float> %tmp31, float %clamp.i4, i32 1
%tmp33 = insertelement <4 x float> %tmp32, float %clamp.i2, i32 2
%tmp34 = insertelement <4 x float> %tmp33, float 1.000000e+00, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll b/llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll
index 57d3c7fc8bd01..48caabd224930 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll
+++ b/llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll
@@ -49,7 +49,7 @@ IF: ; preds = %LOOP
%clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
%max.0.i1 = call float @llvm.maxnum.f32(float %temp6.0, float 0.000000e+00)
%clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
- %tmp34 = insertelement <4 x float> undef, float %clamp.i, i32 0
+ %tmp34 = insertelement <4 x float> poison, float %clamp.i, i32 0
%tmp35 = insertelement <4 x float> %tmp34, float %clamp.i4, i32 1
%tmp36 = insertelement <4 x float> %tmp35, float %clamp.i2, i32 2
%tmp37 = insertelement <4 x float> %tmp36, float 1.000000e+00, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-fs-loop.ll b/llvm/test/CodeGen/AMDGPU/schedule-fs-loop.ll
index 9f0b2119d0f4e..8380bee02868f 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-fs-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/schedule-fs-loop.ll
@@ -50,7 +50,7 @@ ENDIF: ; preds = %ELSE17, %ELSE, %IF
%clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
%max.0.i1 = call float @llvm.maxnum.f32(float %temp2.0, float 0.000000e+00)
%clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
- %tmp31 = insertelement <4 x float> undef, float %clamp.i, i32 0
+ %tmp31 = insertelement <4 x float> poison, float %clamp.i, i32 0
%tmp32 = insertelement <4 x float> %tmp31, float %clamp.i4, i32 1
%tmp33 = insertelement <4 x float> %tmp32, float %clamp.i2, i32 2
%tmp34 = insertelement <4 x float> %tmp33, float 1.000000e+00, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-if-2.ll b/llvm/test/CodeGen/AMDGPU/schedule-if-2.ll
index 1888df188ac07..d6dc911151f25 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-if-2.ll
+++ b/llvm/test/CodeGen/AMDGPU/schedule-if-2.ll
@@ -62,7 +62,7 @@ ENDIF: ; preds = %IF23, %ELSE, %IF
%temp5.0 = phi float [ %27, %IF ], [ %60, %IF23 ], [ 0.000000e+00, %ELSE ]
%temp6.0 = phi float [ %29, %IF ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF23 ]
%temp7.0 = phi float [ %35, %IF ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF23 ]
- %44 = insertelement <4 x float> undef, float %temp4.0, i32 0
+ %44 = insertelement <4 x float> poison, float %temp4.0, i32 0
%45 = insertelement <4 x float> %44, float %temp5.0, i32 1
%46 = insertelement <4 x float> %45, float %temp6.0, i32 2
%47 = insertelement <4 x float> %46, float %temp7.0, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-if.ll b/llvm/test/CodeGen/AMDGPU/schedule-if.ll
index 0e2a82d57044b..0d3891db5e4b3 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-if.ll
+++ b/llvm/test/CodeGen/AMDGPU/schedule-if.ll
@@ -28,7 +28,7 @@ ENDIF: ; preds = %IF13, %ELSE, %main_
%temp.0 = phi float [ 1.000000e+03, %main_body ], [ 1.000000e+00, %IF13 ], [ 0.000000e+00, %ELSE ]
%temp1.0 = phi float [ 0.000000e+00, %main_body ], [ %23, %IF13 ], [ 0.000000e+00, %ELSE ]
%temp3.0 = phi float [ 1.000000e+00, %main_body ], [ 0.000000e+00, %ELSE ], [ 0.000000e+00, %IF13 ]
- %16 = insertelement <4 x float> undef, float %temp.0, i32 0
+ %16 = insertelement <4 x float> poison, float %temp.0, i32 0
%17 = insertelement <4 x float> %16, float %temp1.0, i32 1
%18 = insertelement <4 x float> %17, float 0.000000e+00, i32 2
%19 = insertelement <4 x float> %18, float %temp3.0, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll b/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
index c7bdbffd22307..c5e04b324cd48 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
+++ b/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll
@@ -96,12 +96,12 @@ ENDIF: ; preds = %main_body, %Flow2
%74 = extractelement <4 x float> %73, i32 3
%75 = fmul float %74, %16
%76 = fadd float %75, %60
- %77 = insertelement <4 x float> undef, float %64, i32 0
+ %77 = insertelement <4 x float> poison, float %64, i32 0
%78 = insertelement <4 x float> %77, float %68, i32 1
%79 = insertelement <4 x float> %78, float %72, i32 2
%80 = insertelement <4 x float> %79, float %76, i32 3
call void @llvm.amdgcn.s.barrier()
- %81 = insertelement <4 x float> undef, float %temp.0, i32 0
+ %81 = insertelement <4 x float> poison, float %temp.0, i32 0
%82 = insertelement <4 x float> %81, float %temp1.0, i32 1
%83 = insertelement <4 x float> %82, float %temp2.0, i32 2
%84 = insertelement <4 x float> %83, float %temp3.0, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop.ll b/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop.ll
index b6c7a03b990fd..4066877bf1797 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop.ll
+++ b/llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop.ll
@@ -81,12 +81,12 @@ ENDIF: ; preds = %ENDIF16, %LOOP, %ma
%68 = extractelement <4 x float> %67, i32 3
%69 = fmul float %68, %3
%70 = fadd float %69, %54
- %71 = insertelement <4 x float> undef, float %58, i32 0
+ %71 = insertelement <4 x float> poison, float %58, i32 0
%72 = insertelement <4 x float> %71, float %62, i32 1
%73 = insertelement <4 x float> %72, float %66, i32 2
%74 = insertelement <4 x float> %73, float %70, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %74, i32 60, i32 1)
- %75 = insertelement <4 x float> undef, float %temp.0, i32 0
+ %75 = insertelement <4 x float> poison, float %temp.0, i32 0
%76 = insertelement <4 x float> %75, float %temp1.0, i32 1
%77 = insertelement <4 x float> %76, float %temp2.0, i32 2
%78 = insertelement <4 x float> %77, float %temp3.0, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll b/llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
index 1c912d09c47d1..b84163aa427ae 100644
--- a/llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll
@@ -19,11 +19,11 @@ main_body:
%tmp1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 24, i32 0)
%tmp2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> undef, i32 48, i32 0)
%array_vector3 = insertelement <4 x float> zeroinitializer, float %tmp2, i32 3
- %array_vector5 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %tmp, i32 1
- %array_vector6 = insertelement <4 x float> %array_vector5, float undef, i32 2
- %array_vector9 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %tmp1, i32 1
+ %array_vector5 = insertelement <4 x float> <float 0.000000e+00, float poison, float poison, float poison>, float %tmp, i32 1
+ %array_vector6 = insertelement <4 x float> %array_vector5, float poison, i32 2
+ %array_vector9 = insertelement <4 x float> <float 0.000000e+00, float poison, float poison, float poison>, float %tmp1, i32 1
%array_vector10 = insertelement <4 x float> %array_vector9, float 0.000000e+00, i32 2
- %array_vector11 = insertelement <4 x float> %array_vector10, float undef, i32 3
+ %array_vector11 = insertelement <4 x float> %array_vector10, float poison, i32 3
%tmp3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> undef, i32 undef, i32 4864, i32 0)
call void @llvm.amdgcn.raw.tbuffer.store.i32(i32 %tmp3, <4 x i32> undef, i32 36, i32 %arg, i32 68, i32 3)
%bc = bitcast <4 x float> %array_vector3 to <4 x i32>
@@ -32,9 +32,9 @@ main_body:
%bc49 = bitcast <4 x float> %array_vector11 to <4 x i32>
%tmp5 = extractelement <4 x i32> %bc49, i32 undef
call void @llvm.amdgcn.raw.tbuffer.store.i32(i32 %tmp5, <4 x i32> undef, i32 72, i32 %arg, i32 68, i32 3)
- %array_vector21 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %tmp, i32 1
- %array_vector22 = insertelement <4 x float> %array_vector21, float undef, i32 2
- %array_vector23 = insertelement <4 x float> %array_vector22, float undef, i32 3
+ %array_vector21 = insertelement <4 x float> <float 0.000000e+00, float poison, float poison, float poison>, float %tmp, i32 1
+ %array_vector22 = insertelement <4 x float> %array_vector21, float poison, i32 2
+ %array_vector23 = insertelement <4 x float> %array_vector22, float poison, i32 3
call void @llvm.amdgcn.raw.tbuffer.store.i32(i32 undef, <4 x i32> undef, i32 28, i32 %arg, i32 68, i32 3)
%bc52 = bitcast <4 x float> %array_vector23 to <4 x i32>
%tmp6 = extractelement <4 x i32> %bc52, i32 undef
diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
index 740c6cd6bcc46..80be621999931 100644
--- a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
@@ -1992,13 +1992,13 @@ entry:
%tmp7 = extractelement <8 x i8> %tmp, i32 6
%tmp8 = extractelement <8 x i8> %tmp, i32 7
- %tmp9 = insertelement <2 x i8> undef, i8 %tmp1, i32 0
+ %tmp9 = insertelement <2 x i8> poison, i8 %tmp1, i32 0
%tmp10 = insertelement <2 x i8> %tmp9, i8 %tmp2, i32 1
- %tmp11 = insertelement <2 x i8> undef, i8 %tmp3, i32 0
+ %tmp11 = insertelement <2 x i8> poison, i8 %tmp3, i32 0
%tmp12 = insertelement <2 x i8> %tmp11, i8 %tmp4, i32 1
- %tmp13 = insertelement <2 x i8> undef, i8 %tmp5, i32 0
+ %tmp13 = insertelement <2 x i8> poison, i8 %tmp5, i32 0
%tmp14 = insertelement <2 x i8> %tmp13, i8 %tmp6, i32 1
- %tmp15 = insertelement <2 x i8> undef, i8 %tmp7, i32 0
+ %tmp15 = insertelement <2 x i8> poison, i8 %tmp7, i32 0
%tmp16 = insertelement <2 x i8> %tmp15, i8 %tmp8, i32 1
%tmp17 = shufflevector <2 x i8> %tmp10, <2 x i8> %tmp12, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll b/llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
index 18a20c0bf3f85..849744856f207 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll
@@ -11,7 +11,7 @@ define amdgpu_kernel void @test_dup_operands(ptr addrspace(1) noalias %out, ptr
%lo = extractelement <2 x i32> %a, i32 0
%hi = extractelement <2 x i32> %a, i32 1
%add = add i32 %lo, %lo
- %vec0 = insertelement <2 x i32> undef, i32 %add, i32 0
+ %vec0 = insertelement <2 x i32> poison, i32 %add, i32 0
%vec1 = insertelement <2 x i32> %vec0, i32 %hi, i32 1
store <2 x i32> %vec1, ptr addrspace(1) %out, align 8
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll b/llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll
index e0308bc56d172..7cedbb38cacf7 100644
--- a/llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll
+++ b/llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll
@@ -26,11 +26,11 @@ define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4
%r1 = fadd float %sq1, 2.0
%sq2 = fmul float %w2, %w2
%r2 = fadd float %sq2, 2.0
- %v0 = insertelement <4 x float> undef, float %r0, i32 0
+ %v0 = insertelement <4 x float> poison, float %r0, i32 0
%v1 = insertelement <4 x float> %v0, float %r1, i32 1
%v2 = insertelement <4 x float> %v1, float %r2, i32 2
%res = call float @llvm.r600.dot4(<4 x float> %v2, <4 x float> %v2)
- %vecres = insertelement <4 x float> undef, float %res, i32 0
+ %vecres = insertelement <4 x float> poison, float %res, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %vecres, i32 0, i32 2)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll b/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
index a14c456952db7..b662254fc3db0 100644
--- a/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
+++ b/llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
@@ -234,7 +234,7 @@ main_body:
%tmp128 = load i32, ptr addrspace(3) %tmp118
%tmp129 = bitcast i32 %tmp128 to float
%tmp130 = fsub float %tmp129, %tmp127
- %tmp131 = insertelement <4 x float> undef, float %tmp124, i32 0
+ %tmp131 = insertelement <4 x float> poison, float %tmp124, i32 0
%tmp132 = insertelement <4 x float> %tmp131, float %tmp130, i32 1
%tmp133 = insertelement <4 x float> %tmp132, float %tmp130, i32 2
%tmp134 = insertelement <4 x float> %tmp133, float %tmp130, i32 3
@@ -290,7 +290,7 @@ main_body:
%tmp174 = load i32, ptr addrspace(3) %tmp152
%tmp175 = bitcast i32 %tmp174 to float
%tmp176 = fsub float %tmp175, %tmp173
- %tmp177 = insertelement <4 x float> undef, float %tmp158, i32 0
+ %tmp177 = insertelement <4 x float> poison, float %tmp158, i32 0
%tmp178 = insertelement <4 x float> %tmp177, float %tmp164, i32 1
%tmp179 = insertelement <4 x float> %tmp178, float %tmp170, i32 2
%tmp180 = insertelement <4 x float> %tmp179, float %tmp176, i32 3
@@ -348,7 +348,7 @@ IF: ; preds = %LOOP
%tmp230 = bitcast float %tmp181 to i32
%tmp231 = bitcast float %tmp136 to i32
%tmp232 = bitcast float %tmp182 to i32
- %tmp233 = insertelement <8 x i32> undef, i32 %tmp229, i32 0
+ %tmp233 = insertelement <8 x i32> poison, i32 %tmp229, i32 0
%tmp234 = insertelement <8 x i32> %tmp233, i32 %tmp230, i32 1
%tmp235 = insertelement <8 x i32> %tmp234, i32 %tmp231, i32 2
%tmp236 = insertelement <8 x i32> %tmp235, i32 %tmp232, i32 3
@@ -492,7 +492,7 @@ IF67: ; preds = %LOOP65
%tmp445 = fadd float %tmp444, %tmp439
%tmp446 = fmul float %tmp55, %tmp414
%tmp447 = fadd float %tmp446, %tmp441
- %tmp448 = insertelement <4 x float> undef, float %tmp443, i32 0
+ %tmp448 = insertelement <4 x float> poison, float %tmp443, i32 0
%tmp449 = insertelement <4 x float> %tmp448, float %tmp445, i32 1
%tmp450 = insertelement <4 x float> %tmp449, float %tmp447, i32 2
%tmp451 = insertelement <4 x float> %tmp450, float %tmp194, i32 3
@@ -503,7 +503,7 @@ IF67: ; preds = %LOOP65
%cubesc = call float @llvm.amdgcn.cubesc(float %tmp451.x, float %tmp451.y, float %tmp451.z)
%cubema = call float @llvm.amdgcn.cubema(float %tmp451.x, float %tmp451.y, float %tmp451.z)
%cubeid = call float @llvm.amdgcn.cubeid(float %tmp451.x, float %tmp451.y, float %tmp451.z)
- %tmp452.0 = insertelement <4 x float> undef, float %cubetc, i32 0
+ %tmp452.0 = insertelement <4 x float> poison, float %cubetc, i32 0
%tmp452.1 = insertelement <4 x float> %tmp452.0, float %cubesc, i32 1
%tmp452.2 = insertelement <4 x float> %tmp452.1, float %cubema, i32 2
%tmp452 = insertelement <4 x float> %tmp452.2, float %cubeid, i32 3
@@ -1076,10 +1076,10 @@ LOOP: ; preds = %LOOP, %main_body
%temp170.0 = phi float [ %tmp252, %main_body ], [ %tmp286, %LOOP ]
%tmp276 = bitcast float %temp168.0 to i32
%tmp277 = bitcast float %temp169.0 to i32
- %tmp278 = insertelement <4 x i32> undef, i32 %tmp276, i32 0
+ %tmp278 = insertelement <4 x i32> poison, i32 %tmp276, i32 0
%tmp279 = insertelement <4 x i32> %tmp278, i32 %tmp277, i32 1
%tmp280 = insertelement <4 x i32> %tmp279, i32 0, i32 2
- %tmp281 = insertelement <4 x i32> %tmp280, i32 undef, i32 3
+ %tmp281 = insertelement <4 x i32> %tmp280, i32 poison, i32 3
%tmp148.bc = bitcast <4 x i32> %tmp148 to <4 x i32>
%tmp281.bc = bitcast <4 x i32> %tmp281 to <4 x float>
%tmp282 = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32 15, float %temp168.0, float %temp169.0, float 0.0, <8 x i32> %tmp146, <4 x i32> %tmp148.bc, i1 0, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll b/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
index 8fec79a7efd9b..1b4a3af796bcd 100644
--- a/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
+++ b/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
@@ -316,7 +316,7 @@ define amdgpu_vs void @reorder_local_load_tbuffer_store_local_load(ptr addrspace
%tmp1 = load i32, ptr addrspace(3) %ptr1, align 4
- %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0
+ %vdata = insertelement <4 x i32> poison, i32 %a1, i32 0
%vaddr.add = add i32 %vaddr, 32
call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %vdata, ptr addrspace(8) undef, i32 %vaddr.add, i32 0, i32 0, i32 228, i32 3)
diff --git a/llvm/test/CodeGen/AMDGPU/si-vector-hang.ll b/llvm/test/CodeGen/AMDGPU/si-vector-hang.ll
index 99efc0eb60d17..ee843dc2069d9 100644
--- a/llvm/test/CodeGen/AMDGPU/si-vector-hang.ll
+++ b/llvm/test/CodeGen/AMDGPU/si-vector-hang.ll
@@ -15,7 +15,7 @@
define amdgpu_kernel void @test_8_min_char(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture readonly %in0, ptr addrspace(1) nocapture readonly %in1) #0 {
entry:
%0 = load i8, ptr addrspace(1) %in0, align 1
- %1 = insertelement <8 x i8> undef, i8 %0, i32 0
+ %1 = insertelement <8 x i8> poison, i8 %0, i32 0
%arrayidx2.i.i = getelementptr inbounds i8, ptr addrspace(1) %in0, i64 1
%2 = load i8, ptr addrspace(1) %arrayidx2.i.i, align 1
%3 = insertelement <8 x i8> %1, i8 %2, i32 1
@@ -27,7 +27,7 @@ entry:
%7 = insertelement <8 x i8> %5, i8 %6, i32 3
%arrayidx.i.i = getelementptr inbounds i8, ptr addrspace(1) %in0, i64 4
%8 = load i8, ptr addrspace(1) %arrayidx.i.i, align 1
- %9 = insertelement <8 x i8> undef, i8 %8, i32 0
+ %9 = insertelement <8 x i8> poison, i8 %8, i32 0
%arrayidx2.i9.i = getelementptr inbounds i8, ptr addrspace(1) %in0, i64 5
%10 = load i8, ptr addrspace(1) %arrayidx2.i9.i, align 1
%11 = insertelement <8 x i8> %9, i8 %10, i32 1
@@ -39,7 +39,7 @@ entry:
%15 = insertelement <8 x i8> %13, i8 %14, i32 3
%vecinit5.i = shufflevector <8 x i8> %7, <8 x i8> %15, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
%16 = load i8, ptr addrspace(1) %in1, align 1
- %17 = insertelement <8 x i8> undef, i8 %16, i32 0
+ %17 = insertelement <8 x i8> poison, i8 %16, i32 0
%arrayidx2.i.i4 = getelementptr inbounds i8, ptr addrspace(1) %in1, i64 1
%18 = load i8, ptr addrspace(1) %arrayidx2.i.i4, align 1
%19 = insertelement <8 x i8> %17, i8 %18, i32 1
@@ -51,7 +51,7 @@ entry:
%23 = insertelement <8 x i8> %21, i8 %22, i32 3
%arrayidx.i.i7 = getelementptr inbounds i8, ptr addrspace(1) %in1, i64 4
%24 = load i8, ptr addrspace(1) %arrayidx.i.i7, align 1
- %25 = insertelement <8 x i8> undef, i8 %24, i32 0
+ %25 = insertelement <8 x i8> poison, i8 %24, i32 0
%arrayidx2.i9.i8 = getelementptr inbounds i8, ptr addrspace(1) %in1, i64 5
%26 = load i8, ptr addrspace(1) %arrayidx2.i9.i8, align 1
%27 = insertelement <8 x i8> %25, i8 %26, i32 1
diff --git a/llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll b/llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll
index 20e418bbb4bc6..a266c6385e8c8 100644
--- a/llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll
+++ b/llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll
@@ -4,11 +4,11 @@
; CHECK-LABEL: @test_insertelement(
; CHECK: %alloca = alloca i16
-; CHECK-NEXT: insertelement <2 x ptr addrspace(5)> undef, ptr addrspace(5) %alloca, i32 0
+; CHECK-NEXT: insertelement <2 x ptr addrspace(5)> poison, ptr addrspace(5) %alloca, i32 0
define amdgpu_kernel void @test_insertelement() #0 {
entry:
%alloca = alloca i16, align 4, addrspace(5)
- %in = insertelement <2 x ptr addrspace(5)> undef, ptr addrspace(5) %alloca, i32 0
+ %in = insertelement <2 x ptr addrspace(5)> poison, ptr addrspace(5) %alloca, i32 0
store <2 x ptr addrspace(5)> %in, ptr undef, align 4
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll b/llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
index 899ec36e9b2fe..d8c015b85584a 100644
--- a/llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll
@@ -35,9 +35,9 @@ entry:
%1 = load i32, ptr addrspace(1) %arrayidx1
%2 = load i32, ptr addrspace(1) %arrayidx2
%3 = load i32, ptr addrspace(1) %arrayidx3
- %src1.0 = insertelement <2 x i32> undef, i32 %0, i64 0
+ %src1.0 = insertelement <2 x i32> poison, i32 %0, i64 0
%src1 = insertelement <2 x i32> %src1.0, i32 %1, i64 1
- %src2.0 = insertelement <4 x i32> undef, i32 %2, i64 0
+ %src2.0 = insertelement <4 x i32> poison, i32 %2, i64 0
%src2.1 = insertelement <4 x i32> %src2.0, i32 %3, i64 1
%src2.2 = insertelement <4 x i32> %src2.1, i32 %3, i64 2
%src2 = insertelement <4 x i32> %src2.2, i32 %3, i64 3
diff --git a/llvm/test/CodeGen/AMDGPU/sminmax.ll b/llvm/test/CodeGen/AMDGPU/sminmax.ll
index 65ae200275a0e..78ce539808306 100644
--- a/llvm/test/CodeGen/AMDGPU/sminmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/sminmax.ll
@@ -65,9 +65,9 @@ define amdgpu_kernel void @v_abs_i32_repeat_user(ptr addrspace(1) %out, ptr addr
; EG: MAX_INT
; EG: MAX_INT
define amdgpu_kernel void @s_abs_v2i32(ptr addrspace(1) %out, <2 x i32> %val) nounwind {
- %z0 = insertelement <2 x i32> undef, i32 0, i32 0
+ %z0 = insertelement <2 x i32> poison, i32 0, i32 0
%z1 = insertelement <2 x i32> %z0, i32 0, i32 1
- %t0 = insertelement <2 x i32> undef, i32 2, i32 0
+ %t0 = insertelement <2 x i32> poison, i32 2, i32 0
%t1 = insertelement <2 x i32> %t0, i32 2, i32 1
%neg = sub <2 x i32> %z1, %val
%cond = icmp sgt <2 x i32> %val, %neg
@@ -96,9 +96,9 @@ define amdgpu_kernel void @s_abs_v2i32(ptr addrspace(1) %out, <2 x i32> %val) no
; EG: MAX_INT
; EG: MAX_INT
define amdgpu_kernel void @v_abs_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %src) nounwind {
- %z0 = insertelement <2 x i32> undef, i32 0, i32 0
+ %z0 = insertelement <2 x i32> poison, i32 0, i32 0
%z1 = insertelement <2 x i32> %z0, i32 0, i32 1
- %t0 = insertelement <2 x i32> undef, i32 2, i32 0
+ %t0 = insertelement <2 x i32> poison, i32 2, i32 0
%t1 = insertelement <2 x i32> %t0, i32 2, i32 1
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.in = getelementptr inbounds <2 x i32>, ptr addrspace(1) %src, i32 %tid
@@ -128,11 +128,11 @@ define amdgpu_kernel void @v_abs_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %
; EG: MAX_INT
; EG: MAX_INT
define amdgpu_kernel void @s_abs_v4i32(ptr addrspace(1) %out, <4 x i32> %val) nounwind {
- %z0 = insertelement <4 x i32> undef, i32 0, i32 0
+ %z0 = insertelement <4 x i32> poison, i32 0, i32 0
%z1 = insertelement <4 x i32> %z0, i32 0, i32 1
%z2 = insertelement <4 x i32> %z1, i32 0, i32 2
%z3 = insertelement <4 x i32> %z2, i32 0, i32 3
- %t0 = insertelement <4 x i32> undef, i32 2, i32 0
+ %t0 = insertelement <4 x i32> poison, i32 2, i32 0
%t1 = insertelement <4 x i32> %t0, i32 2, i32 1
%t2 = insertelement <4 x i32> %t1, i32 2, i32 2
%t3 = insertelement <4 x i32> %t2, i32 2, i32 3
@@ -176,11 +176,11 @@ define amdgpu_kernel void @s_abs_v4i32(ptr addrspace(1) %out, <4 x i32> %val) no
; EG: MAX_INT
; EG: MAX_INT
define amdgpu_kernel void @v_abs_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %src) nounwind {
- %z0 = insertelement <4 x i32> undef, i32 0, i32 0
+ %z0 = insertelement <4 x i32> poison, i32 0, i32 0
%z1 = insertelement <4 x i32> %z0, i32 0, i32 1
%z2 = insertelement <4 x i32> %z1, i32 0, i32 2
%z3 = insertelement <4 x i32> %z2, i32 0, i32 3
- %t0 = insertelement <4 x i32> undef, i32 2, i32 0
+ %t0 = insertelement <4 x i32> poison, i32 2, i32 0
%t1 = insertelement <4 x i32> %t0, i32 2, i32 1
%t2 = insertelement <4 x i32> %t1, i32 2, i32 2
%t3 = insertelement <4 x i32> %t2, i32 2, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
index 71033cfd1a6f3..ff93d6f7c3961 100644
--- a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
@@ -215,9 +215,9 @@ define amdgpu_kernel void @s_abs_v2i16_2(ptr addrspace(1) %out, <2 x i16> %val)
; CI-NEXT: v_mov_b32_e32 v0, s4
; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; CI-NEXT: s_endpgm
- %z0 = insertelement <2 x i16> undef, i16 0, i16 0
+ %z0 = insertelement <2 x i16> poison, i16 0, i16 0
%z1 = insertelement <2 x i16> %z0, i16 0, i16 1
- %t0 = insertelement <2 x i16> undef, i16 2, i16 0
+ %t0 = insertelement <2 x i16> poison, i16 2, i16 0
%t1 = insertelement <2 x i16> %t0, i16 2, i16 1
%neg = sub <2 x i16> %z1, %val
%cond = icmp sgt <2 x i16> %val, %neg
@@ -297,9 +297,9 @@ define amdgpu_kernel void @v_abs_v2i16_2(ptr addrspace(1) %out, ptr addrspace(1)
; CI-NEXT: v_add_i32_e32 v0, vcc, 0x20000, v0
; CI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; CI-NEXT: s_endpgm
- %z0 = insertelement <2 x i16> undef, i16 0, i16 0
+ %z0 = insertelement <2 x i16> poison, i16 0, i16 0
%z1 = insertelement <2 x i16> %z0, i16 0, i16 1
- %t0 = insertelement <2 x i16> undef, i16 2, i16 0
+ %t0 = insertelement <2 x i16> poison, i16 2, i16 0
%t1 = insertelement <2 x i16> %t0, i16 2, i16 1
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.in = getelementptr inbounds <2 x i16>, ptr addrspace(1) %src, i32 %tid
@@ -406,11 +406,11 @@ define amdgpu_kernel void @s_abs_v4i16(ptr addrspace(1) %out, <4 x i16> %val) #0
; CI-NEXT: v_mov_b32_e32 v1, s0
; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; CI-NEXT: s_endpgm
- %z0 = insertelement <4 x i16> undef, i16 0, i16 0
+ %z0 = insertelement <4 x i16> poison, i16 0, i16 0
%z1 = insertelement <4 x i16> %z0, i16 0, i16 1
%z2 = insertelement <4 x i16> %z1, i16 0, i16 2
%z3 = insertelement <4 x i16> %z2, i16 0, i16 3
- %t0 = insertelement <4 x i16> undef, i16 2, i16 0
+ %t0 = insertelement <4 x i16> poison, i16 2, i16 0
%t1 = insertelement <4 x i16> %t0, i16 2, i16 1
%t2 = insertelement <4 x i16> %t1, i16 2, i16 2
%t3 = insertelement <4 x i16> %t2, i16 2, i16 3
@@ -518,11 +518,11 @@ define amdgpu_kernel void @v_abs_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %
; CI-NEXT: v_add_i32_e32 v0, vcc, 0x20000, v0
; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; CI-NEXT: s_endpgm
- %z0 = insertelement <4 x i16> undef, i16 0, i16 0
+ %z0 = insertelement <4 x i16> poison, i16 0, i16 0
%z1 = insertelement <4 x i16> %z0, i16 0, i16 1
%z2 = insertelement <4 x i16> %z1, i16 0, i16 2
%z3 = insertelement <4 x i16> %z2, i16 0, i16 3
- %t0 = insertelement <4 x i16> undef, i16 2, i16 0
+ %t0 = insertelement <4 x i16> poison, i16 2, i16 0
%t1 = insertelement <4 x i16> %t0, i16 2, i16 1
%t2 = insertelement <4 x i16> %t1, i16 2, i16 2
%t3 = insertelement <4 x i16> %t2, i16 2, i16 3
diff --git a/llvm/test/CodeGen/AMDGPU/smrd.ll b/llvm/test/CodeGen/AMDGPU/smrd.ll
index 52db7fea08e05..ae398cc800ff0 100644
--- a/llvm/test/CodeGen/AMDGPU/smrd.ll
+++ b/llvm/test/CodeGen/AMDGPU/smrd.ll
@@ -125,7 +125,7 @@ entry:
; GCN-NEXT: s_buffer_load_dword s0, s[0:3], 0x0
define amdgpu_ps float @smrd_hazard(<4 x i32> inreg %desc) #0 {
main_body:
- %d0 = insertelement <4 x i32> undef, i32 0, i32 0
+ %d0 = insertelement <4 x i32> poison, i32 0, i32 0
%d1 = insertelement <4 x i32> %d0, i32 1, i32 1
%d2 = insertelement <4 x i32> %d1, i32 2, i32 2
%d3 = insertelement <4 x i32> %d2, i32 3, i32 3
@@ -419,7 +419,7 @@ main_body:
%v0.y = call nsz float @llvm.amdgcn.interp.p2(float %v0.y1, float %v, i32 0, i32 1, i32 %prim)
%v0.z1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 0, i32 2, i32 %prim)
%v0.z = call nsz float @llvm.amdgcn.interp.p2(float %v0.z1, float %v, i32 0, i32 2, i32 %prim)
- %v0.tmp0 = insertelement <3 x float> undef, float %v0.x, i32 0
+ %v0.tmp0 = insertelement <3 x float> poison, float %v0.x, i32 0
%v0.tmp1 = insertelement <3 x float> %v0.tmp0, float %v0.y, i32 1
%v0 = insertelement <3 x float> %v0.tmp1, float %v0.z, i32 2
%a = extractelement <3 x float> %v0, i32 %idx1
@@ -430,7 +430,7 @@ main_body:
%v1.y = call nsz float @llvm.amdgcn.interp.p2(float %v1.y1, float %v, i32 1, i32 1, i32 %prim)
%v1.z1 = call nsz float @llvm.amdgcn.interp.p1(float %u, i32 1, i32 2, i32 %prim)
%v1.z = call nsz float @llvm.amdgcn.interp.p2(float %v1.z1, float %v, i32 1, i32 2, i32 %prim)
- %v1.tmp0 = insertelement <3 x float> undef, float %v0.x, i32 0
+ %v1.tmp0 = insertelement <3 x float> poison, float %v0.x, i32 0
%v1.tmp1 = insertelement <3 x float> %v0.tmp0, float %v0.y, i32 1
%v1 = insertelement <3 x float> %v0.tmp1, float %v0.z, i32 2
diff --git a/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll b/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
index 03e8e28ef54db..aaf2e1dd604fa 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
@@ -18,7 +18,7 @@ define amdgpu_kernel void @test_spill_av_class(<4 x i32> %arg) #0 {
; GCN-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3538953 /* reguse:VReg_64 */, %13
; GCN-NEXT: S_ENDPGM 0
%v0 = call i32 asm sideeffect "; def $0", "=v"()
- %tmp = insertelement <2 x i32> undef, i32 %v0, i32 0
+ %tmp = insertelement <2 x i32> poison, i32 %v0, i32 0
%mai = tail call <4 x i32> @llvm.amdgcn.mfma.i32.4x4x4i8(i32 1, i32 2, <4 x i32> %arg, i32 0, i32 0, i32 0)
store volatile <4 x i32> %mai, ptr addrspace(1) undef
call void asm sideeffect "; use $0", "v"(<2 x i32> %tmp);
diff --git a/llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll b/llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
index 22ed0f37c1b3d..00c2a9d96dc85 100644
--- a/llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
+++ b/llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
@@ -15,7 +15,7 @@ declare i32 @llvm.amdgcn.workitem.id.x() readnone
; SI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
define amdgpu_kernel void @imp_def_vcc_split_i64_add_0(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %s.val) {
%v.val = load volatile i32, ptr addrspace(1) %in
- %vec.0 = insertelement <2 x i32> undef, i32 %s.val, i32 0
+ %vec.0 = insertelement <2 x i32> poison, i32 %s.val, i32 0
%vec.1 = insertelement <2 x i32> %vec.0, i32 %v.val, i32 1
%bc = bitcast <2 x i32> %vec.1 to i64
%add = add i64 %bc, 399
@@ -27,7 +27,7 @@ define amdgpu_kernel void @imp_def_vcc_split_i64_add_0(ptr addrspace(1) %out, pt
; SI: s_add_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x18f
; SI: s_addc_u32 {{s[0-9]+}}, 0xf423f, 0
define amdgpu_kernel void @s_imp_def_vcc_split_i64_add_0(ptr addrspace(1) %out, i32 %val) {
- %vec.0 = insertelement <2 x i32> undef, i32 %val, i32 0
+ %vec.0 = insertelement <2 x i32> poison, i32 %val, i32 0
%vec.1 = insertelement <2 x i32> %vec.0, i32 999999, i32 1
%bc = bitcast <2 x i32> %vec.1 to i64
%add = add i64 %bc, 399
@@ -40,7 +40,7 @@ define amdgpu_kernel void @s_imp_def_vcc_split_i64_add_0(ptr addrspace(1) %out,
; SI: v_addc_u32
define amdgpu_kernel void @imp_def_vcc_split_i64_add_1(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %val0, i64 %val1) {
%v.val = load volatile i32, ptr addrspace(1) %in
- %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0
+ %vec.0 = insertelement <2 x i32> poison, i32 %val0, i32 0
%vec.1 = insertelement <2 x i32> %vec.0, i32 %v.val, i32 1
%bc = bitcast <2 x i32> %vec.1 to i64
%add = add i64 %bc, %val1
@@ -52,7 +52,7 @@ define amdgpu_kernel void @imp_def_vcc_split_i64_add_1(ptr addrspace(1) %out, pt
; SI: s_add_u32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
; SI: s_addc_u32 {{s[0-9]+}}, 0x1869f, {{s[0-9]+}}
define amdgpu_kernel void @s_imp_def_vcc_split_i64_add_1(ptr addrspace(1) %out, i32 %val0, i64 %val1) {
- %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0
+ %vec.0 = insertelement <2 x i32> poison, i32 %val0, i32 0
%vec.1 = insertelement <2 x i32> %vec.0, i32 99999, i32 1
%bc = bitcast <2 x i32> %vec.1 to i64
%add = add i64 %bc, %val1
@@ -68,7 +68,7 @@ define amdgpu_kernel void @imp_def_vcc_split_i64_add_2(ptr addrspace(1) %out, pt
%tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
%gep = getelementptr i32, ptr addrspace(1) %in, i32 %tid
%load = load i32, ptr addrspace(1) %gep
- %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0
+ %vec.0 = insertelement <2 x i32> poison, i32 %val0, i32 0
%vec.1 = insertelement <2 x i32> %vec.0, i32 %load, i32 1
%bc = bitcast <2 x i32> %vec.1 to i64
%add = add i64 %bc, %val1
diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
index c611c4b502817..64bbdb34b7d14 100644
--- a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
+++ b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
@@ -375,28 +375,28 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x
%12 = extractelement <31 x i32> %userData, i64 24
%13 = extractelement <31 x i32> %userData, i64 26
%14 = extractelement <31 x i32> %userData, i64 30
- %15 = insertelement <2 x i32> undef, i32 %13, i32 0
+ %15 = insertelement <2 x i32> poison, i32 %13, i32 0
%16 = bitcast <2 x i32> %15 to i64
%17 = inttoptr i64 %16 to ptr addrspace(4)
- %18 = insertelement <2 x i32> undef, i32 %12, i32 0
+ %18 = insertelement <2 x i32> poison, i32 %12, i32 0
%19 = bitcast <2 x i32> %18 to i64
%20 = inttoptr i64 %19 to ptr addrspace(4)
- %21 = insertelement <2 x i32> undef, i32 %11, i32 0
+ %21 = insertelement <2 x i32> poison, i32 %11, i32 0
%22 = bitcast <2 x i32> %21 to i64
- %23 = insertelement <2 x i32> undef, i32 %10, i32 0
+ %23 = insertelement <2 x i32> poison, i32 %10, i32 0
%24 = bitcast <2 x i32> %23 to i64
- %25 = insertelement <2 x i32> undef, i32 %9, i32 0
+ %25 = insertelement <2 x i32> poison, i32 %9, i32 0
%26 = bitcast <2 x i32> %25 to i64
%27 = inttoptr i64 %26 to ptr addrspace(4)
- %28 = insertelement <2 x i32> undef, i32 %8, i32 0
+ %28 = insertelement <2 x i32> poison, i32 %8, i32 0
%29 = bitcast <2 x i32> %28 to i64
- %30 = insertelement <2 x i32> undef, i32 %7, i32 0
+ %30 = insertelement <2 x i32> poison, i32 %7, i32 0
%31 = bitcast <2 x i32> %30 to i64
%32 = inttoptr i64 %31 to ptr addrspace(4)
- %33 = insertelement <2 x i32> undef, i32 %6, i32 0
+ %33 = insertelement <2 x i32> poison, i32 %6, i32 0
%34 = bitcast <2 x i32> %33 to i64
%35 = inttoptr i64 %34 to ptr addrspace(4)
- %36 = insertelement <2 x i32> undef, i32 %14, i32 0
+ %36 = insertelement <2 x i32> poison, i32 %14, i32 0
%37 = bitcast <2 x i32> %36 to i64
%38 = inttoptr i64 %37 to ptr addrspace(4)
%39 = getelementptr i8, ptr addrspace(4) %38, i64 232
@@ -404,10 +404,10 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x
%.i184.i = getelementptr i8, ptr addrspace(4) %38, i64 236
%rootDesc58.ii1.i = load i32, ptr addrspace(4) %.i184.i, align 4
%40 = and i32 %rootDesc58.ii1.i, 65535
- %41 = insertelement <4 x i32> <i32 undef, i32 undef, i32 -1, i32 553734060>, i32 %rootDesc58.ii0.i, i32 0
+ %41 = insertelement <4 x i32> <i32 poison, i32 poison, i32 -1, i32 553734060>, i32 %rootDesc58.ii0.i, i32 0
%42 = insertelement <4 x i32> %41, i32 %40, i32 1
%43 = and i32 undef, 65535
- %44 = insertelement <4 x i32> undef, i32 %43, i32 1
+ %44 = insertelement <4 x i32> poison, i32 %43, i32 1
%45 = load <4 x i32>, ptr addrspace(4) undef, align 16
%46 = call i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32> %45, i32 0, i32 0, i32 0, i32 0)
%47 = add i32 %46, -1
@@ -662,7 +662,7 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x
%296 = getelementptr i8, ptr addrspace(4) %293, i64 %295
%.ii0.i = load i32, ptr addrspace(4) %296, align 8
%297 = and i32 undef, 65535
- %298 = insertelement <4 x i32> <i32 undef, i32 undef, i32 -1, i32 553734060>, i32 %.ii0.i, i32 0
+ %298 = insertelement <4 x i32> <i32 poison, i32 poison, i32 -1, i32 553734060>, i32 %.ii0.i, i32 0
%299 = insertelement <4 x i32> %298, i32 %297, i32 1
%300 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %299, i32 0, i32 0)
%301 = add i32 %300, -467
@@ -674,7 +674,7 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x
%.i191.i = getelementptr i8, ptr addrspace(4) %305, i64 4
%.ii192.i = load i32, ptr addrspace(4) %.i191.i, align 4
%306 = and i32 %.ii192.i, 65535
- %307 = insertelement <4 x i32> <i32 undef, i32 undef, i32 -1, i32 553734060>, i32 %.ii090.i, i32 0
+ %307 = insertelement <4 x i32> <i32 poison, i32 poison, i32 -1, i32 553734060>, i32 %.ii090.i, i32 0
%308 = insertelement <4 x i32> %307, i32 %306, i32 1
%309 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %308, i32 0, i32 0)
%310 = add i32 %309, -468
@@ -686,7 +686,7 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x
%.i197.i = getelementptr i8, ptr addrspace(4) %314, i64 4
%.ii198.i = load i32, ptr addrspace(4) %.i197.i, align 4
%315 = and i32 %.ii198.i, 65535
- %316 = insertelement <4 x i32> <i32 undef, i32 undef, i32 -1, i32 553734060>, i32 %.ii096.i, i32 0
+ %316 = insertelement <4 x i32> <i32 poison, i32 poison, i32 -1, i32 553734060>, i32 %.ii096.i, i32 0
%317 = insertelement <4 x i32> %316, i32 %315, i32 1
%318 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %317, i32 0, i32 0)
%319 = add i32 %318, -469
@@ -698,7 +698,7 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x
%.ii0102.i = load i32, ptr addrspace(4) %324, align 8
%.ii1104.i = load i32, ptr addrspace(4) undef, align 4
%325 = and i32 %.ii1104.i, 65535
- %326 = insertelement <4 x i32> <i32 undef, i32 undef, i32 -1, i32 553734060>, i32 %.ii0102.i, i32 0
+ %326 = insertelement <4 x i32> <i32 poison, i32 poison, i32 -1, i32 553734060>, i32 %.ii0102.i, i32 0
%327 = insertelement <4 x i32> %326, i32 %325, i32 1
%328 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %327, i32 0, i32 0)
%329 = add i32 %328, -473
@@ -755,7 +755,7 @@ define amdgpu_gs void @_amdgpu_gs_main(i32 inreg %primShaderTableAddrLow, <31 x
%.not.i = icmp eq i32 %379, 0
%380 = load <8 x i32>, ptr addrspace(4) undef, align 32
%.i010.i = select i1 %.not.i, float 0x36A0000000000000, float 0.000000e+00
- %381 = insertelement <4 x float> undef, float %.i010.i, i32 3
+ %381 = insertelement <4 x float> poison, float %.i010.i, i32 3
call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %381, i32 15, i32 undef, i32 undef, <8 x i32> %380, i32 0, i32 0)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/sram-ecc-default.ll b/llvm/test/CodeGen/AMDGPU/sram-ecc-default.ll
index b0154279f4ae1..88ca0306ae7d1 100644
--- a/llvm/test/CodeGen/AMDGPU/sram-ecc-default.ll
+++ b/llvm/test/CodeGen/AMDGPU/sram-ecc-default.ll
@@ -17,7 +17,7 @@ define void @load_global_hi_v2i16_reglo_vreg(ptr addrspace(1) %in, i16 %reg) {
entry:
%gep = getelementptr inbounds i16, ptr addrspace(1) %in, i64 -2047
%load = load i16, ptr addrspace(1) %gep
- %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
+ %build0 = insertelement <2 x i16> poison, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, ptr addrspace(1) undef
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
index 4af283775aa77..f6d67aa2d5df3 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
@@ -7,31 +7,31 @@ entry:
br i1 undef, label %for.inc.1, label %do.body.preheader
do.body.preheader: ; preds = %entry
- %tmp = insertelement <4 x i32> zeroinitializer, i32 undef, i32 1
+ %tmp = insertelement <4 x i32> zeroinitializer, i32 poison, i32 1
br i1 undef, label %do.body56.1, label %do.body90
do.body90: ; preds = %do.body56.2, %do.body56.1, %do.body.preheader
%tmp1 = phi <4 x i32> [ %tmp6, %do.body56.2 ], [ %tmp5, %do.body56.1 ], [ %tmp, %do.body.preheader ]
- %tmp2 = insertelement <4 x i32> %tmp1, i32 undef, i32 2
- %tmp3 = insertelement <4 x i32> %tmp2, i32 undef, i32 3
+ %tmp2 = insertelement <4 x i32> %tmp1, i32 poison, i32 2
+ %tmp3 = insertelement <4 x i32> %tmp2, i32 poison, i32 3
br i1 undef, label %do.body124.1, label %do.body.1562.preheader
do.body.1562.preheader: ; preds = %do.body124.1, %do.body90
%storemerge = phi <4 x i32> [ %tmp3, %do.body90 ], [ %tmp7, %do.body124.1 ]
- %tmp4 = insertelement <4 x i32> undef, i32 undef, i32 1
+ %tmp4 = insertelement <4 x i32> poison, i32 poison, i32 1
br label %for.inc.1
do.body56.1: ; preds = %do.body.preheader
- %tmp5 = insertelement <4 x i32> %tmp, i32 undef, i32 1
+ %tmp5 = insertelement <4 x i32> %tmp, i32 poison, i32 1
%or.cond472.1 = or i1 undef, undef
br i1 %or.cond472.1, label %do.body56.2, label %do.body90
do.body56.2: ; preds = %do.body56.1
- %tmp6 = insertelement <4 x i32> %tmp5, i32 undef, i32 1
+ %tmp6 = insertelement <4 x i32> %tmp5, i32 poison, i32 1
br label %do.body90
do.body124.1: ; preds = %do.body90
- %tmp7 = insertelement <4 x i32> %tmp3, i32 undef, i32 3
+ %tmp7 = insertelement <4 x i32> %tmp3, i32 poison, i32 3
br label %do.body.1562.preheader
for.inc.1: ; preds = %do.body.1562.preheader, %entry
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
index d4329aec2021c..4621be5cab450 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
@@ -40,13 +40,13 @@ define amdgpu_kernel void @foobar(float %a0, float %a1, ptr addrspace(1) %out) #
; Such a copies appear because the float4 vectors and their elements in the test are uniform
; but the PHI node in "ife" block is divergent because of the CF dependency (divergent branch in bb0)
entry:
- %v0 = insertelement <4 x float> undef, float %a0, i32 0
+ %v0 = insertelement <4 x float> poison, float %a0, i32 0
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%cnd = icmp eq i32 %tid, 0
br i1 %cnd, label %ift, label %ife
ift:
- %v1 = insertelement <4 x float> undef, float %a1, i32 0
+ %v1 = insertelement <4 x float> poison, float %a1, i32 0
br label %ife
ife:
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll b/llvm/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll
index f79ca18e7672d..b60eb219081e0 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll
+++ b/llvm/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll
@@ -11,7 +11,7 @@ define amdgpu_kernel void @foobar() {
%v4 = extractelement <4 x i32> %v3, i32 1
%v5 = icmp ne i32 %v4, 0
%v6 = select i1 %v5, i32 undef, i32 0
- %v15 = insertelement <2 x i32> undef, i32 %v6, i32 1
+ %v15 = insertelement <2 x i32> poison, i32 %v6, i32 1
store <2 x i32> %v15, ptr addrspace(1) undef, align 8
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/swizzle-export.ll b/llvm/test/CodeGen/AMDGPU/swizzle-export.ll
index 1adf549c76767..8d5b6568340db 100644
--- a/llvm/test/CodeGen/AMDGPU/swizzle-export.ll
+++ b/llvm/test/CodeGen/AMDGPU/swizzle-export.ll
@@ -64,27 +64,27 @@ main_body:
%53 = load <4 x float>, ptr addrspace(8) null
%54 = extractelement <4 x float> %53, i32 0
%55 = fmul float 1.000000e+00, %54
- %56 = insertelement <4 x float> undef, float %0, i32 0
+ %56 = insertelement <4 x float> poison, float %0, i32 0
%57 = insertelement <4 x float> %56, float %1, i32 1
%58 = insertelement <4 x float> %57, float %2, i32 2
%59 = insertelement <4 x float> %58, float %3, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %59, i32 60, i32 1)
- %60 = insertelement <4 x float> undef, float %10, i32 0
+ %60 = insertelement <4 x float> poison, float %10, i32 0
%61 = insertelement <4 x float> %60, float %13, i32 1
%62 = insertelement <4 x float> %61, float %16, i32 2
%63 = insertelement <4 x float> %62, float %19, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %63, i32 0, i32 2)
- %64 = insertelement <4 x float> undef, float %22, i32 0
+ %64 = insertelement <4 x float> poison, float %22, i32 0
%65 = insertelement <4 x float> %64, float %25, i32 1
%66 = insertelement <4 x float> %65, float %28, i32 2
%67 = insertelement <4 x float> %66, float %31, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %67, i32 1, i32 2)
- %68 = insertelement <4 x float> undef, float %34, i32 0
+ %68 = insertelement <4 x float> poison, float %34, i32 0
%69 = insertelement <4 x float> %68, float %37, i32 1
%70 = insertelement <4 x float> %69, float %40, i32 2
%71 = insertelement <4 x float> %70, float %43, i32 3
call void @llvm.r600.store.swizzle(<4 x float> %71, i32 2, i32 2)
- %72 = insertelement <4 x float> undef, float %46, i32 0
+ %72 = insertelement <4 x float> poison, float %46, i32 0
%73 = insertelement <4 x float> %72, float %49, i32 1
%74 = insertelement <4 x float> %73, float %52, i32 2
%75 = insertelement <4 x float> %74, float %55, i32 3
@@ -109,10 +109,10 @@ main_body:
%8 = extractelement <4 x float> %7, i32 0
%9 = load <4 x float>, ptr addrspace(8) null
%10 = extractelement <4 x float> %9, i32 1
- %11 = insertelement <4 x float> undef, float %2, i32 0
+ %11 = insertelement <4 x float> poison, float %2, i32 0
%12 = insertelement <4 x float> %11, float %3, i32 1
call void @llvm.r600.store.swizzle(<4 x float> %12, i32 60, i32 1)
- %13 = insertelement <4 x float> undef, float %6, i32 0
+ %13 = insertelement <4 x float> poison, float %6, i32 0
%14 = insertelement <4 x float> %13, float %8, i32 1
%15 = insertelement <4 x float> %14, float %10, i32 2
%16 = insertelement <4 x float> %15, float 0.000000e+00, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/tex-clause-antidep.ll b/llvm/test/CodeGen/AMDGPU/tex-clause-antidep.ll
index 6e906446ccc62..63dd9f7bbc4c2 100644
--- a/llvm/test/CodeGen/AMDGPU/tex-clause-antidep.ll
+++ b/llvm/test/CodeGen/AMDGPU/tex-clause-antidep.ll
@@ -8,7 +8,7 @@ define amdgpu_vs void @test(<4 x float> inreg %reg0) {
%2 = extractelement <4 x float> %reg0, i32 1
%3 = extractelement <4 x float> %reg0, i32 2
%4 = extractelement <4 x float> %reg0, i32 3
- %5 = insertelement <4 x float> undef, float %1, i32 0
+ %5 = insertelement <4 x float> poison, float %1, i32 0
%6 = insertelement <4 x float> %5, float %2, i32 1
%7 = insertelement <4 x float> %6, float %3, i32 2
%8 = insertelement <4 x float> %7, float %4, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/texture-input-merge.ll b/llvm/test/CodeGen/AMDGPU/texture-input-merge.ll
index 92aeb6bd428ef..26dce4fe7f993 100644
--- a/llvm/test/CodeGen/AMDGPU/texture-input-merge.ll
+++ b/llvm/test/CodeGen/AMDGPU/texture-input-merge.ll
@@ -11,11 +11,11 @@ define amdgpu_vs void @test(<4 x float> inreg %reg0) {
%6 = fmul float %2, 3.0
%7 = fmul float %3, 3.0
%8 = fmul float %4, 3.0
- %9 = insertelement <4 x float> undef, float %5, i32 0
+ %9 = insertelement <4 x float> poison, float %5, i32 0
%10 = insertelement <4 x float> %9, float %6, i32 1
- %11 = insertelement <4 x float> undef, float %7, i32 0
+ %11 = insertelement <4 x float> poison, float %7, i32 0
%12 = insertelement <4 x float> %11, float %5, i32 1
- %13 = insertelement <4 x float> undef, float %8, i32 0
+ %13 = insertelement <4 x float> poison, float %8, i32 0
%14 = call <4 x float> @llvm.r600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%15 = call <4 x float> @llvm.r600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%16 = call <4 x float> @llvm.r600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/trunc-combine.ll b/llvm/test/CodeGen/AMDGPU/trunc-combine.ll
index 15d172eb17688..0c2adefd0be7c 100644
--- a/llvm/test/CodeGen/AMDGPU/trunc-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/trunc-combine.ll
@@ -45,7 +45,7 @@ define i16 @trunc_bitcast_v2i32_to_i16(<2 x i32> %bar) {
; VI-NEXT: s_setpc_b64 s[30:31]
%load0 = load i32, ptr addrspace(1) undef
%load1 = load i32, ptr addrspace(1) null
- %insert.0 = insertelement <2 x i32> undef, i32 %load0, i32 0
+ %insert.0 = insertelement <2 x i32> poison, i32 %load0, i32 0
%insert.1 = insertelement <2 x i32> %insert.0, i32 99, i32 1
%bc = bitcast <2 x i32> %insert.1 to i64
%trunc = trunc i64 %bc to i16
@@ -74,7 +74,7 @@ define i16 @trunc_bitcast_v2f32_to_i16(<2 x float> %bar) {
; VI-NEXT: s_setpc_b64 s[30:31]
%load0 = load float, ptr addrspace(1) undef
%load1 = load float, ptr addrspace(1) null
- %insert.0 = insertelement <2 x float> undef, float %load0, i32 0
+ %insert.0 = insertelement <2 x float> poison, float %load0, i32 0
%insert.1 = insertelement <2 x float> %insert.0, float 4.0, i32 1
%bc = bitcast <2 x float> %insert.1 to i64
%trunc = trunc i64 %bc to i16
@@ -128,8 +128,8 @@ bb:
%tmp8 = extractelement <2 x i32> %tmp6, i64 0
%tmp9 = extractelement <2 x i32> %tmp7, i64 0
%tmp10 = mul nsw i32 %tmp9, %tmp8
- %tmp11 = insertelement <2 x i32> undef, i32 %tmp10, i32 0
- %tmp12 = insertelement <2 x i32> %tmp11, i32 undef, i32 1
+ %tmp11 = insertelement <2 x i32> poison, i32 %tmp10, i32 0
+ %tmp12 = insertelement <2 x i32> %tmp11, i32 poison, i32 1
%tmp13 = lshr <2 x i32> %tmp12, <i32 16, i32 16>
%tmp14 = trunc <2 x i32> %tmp13 to <2 x i16>
%tmp15 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %arg2, i64 undef
diff --git a/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
index 0acee5bd5ac19..2809234ce8941 100644
--- a/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
+++ b/llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
@@ -69,7 +69,7 @@ define amdgpu_ps float @valley_partially_undef_copy() #0 {
bb:
%tmp = load volatile i32, ptr addrspace(1) undef, align 4
%tmp1 = load volatile i32, ptr addrspace(1) undef, align 4
- %tmp2 = insertelement <4 x i32> undef, i32 %tmp1, i32 0
+ %tmp2 = insertelement <4 x i32> poison, i32 %tmp1, i32 0
%tmp3 = bitcast i32 %tmp1 to float
%tmp4 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp3, float %tmp3, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
%tmp5 = extractelement <4 x float> %tmp4, i32 0
@@ -115,7 +115,7 @@ define amdgpu_kernel void @partially_undef_copy() #0 {
%tmp0 = call i32 asm sideeffect "v_mov_b32_e32 v5, 5", "={v5}"()
%tmp1 = call i32 asm sideeffect "v_mov_b32_e32 v6, 6", "={v6}"()
- %partially.undef.0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
+ %partially.undef.0 = insertelement <4 x i32> poison, i32 %tmp0, i32 0
%partially.undef.1 = insertelement <4 x i32> %partially.undef.0, i32 %tmp1, i32 0
store volatile <4 x i32> %partially.undef.1, ptr addrspace(1) undef, align 16
diff --git a/llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll b/llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
index 08c06b0029ff2..2d780c86c4566 100644
--- a/llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
@@ -44,7 +44,7 @@ main_body:
%tmp50 = bitcast float %tmp27 to i32
%tmp51 = bitcast float %tmp48 to i32
%tmp52 = bitcast float %tmp49 to i32
- %tmp53 = insertelement <4 x i32> undef, i32 %tmp50, i32 0
+ %tmp53 = insertelement <4 x i32> poison, i32 %tmp50, i32 0
%tmp54 = insertelement <4 x i32> %tmp53, i32 %tmp51, i32 1
%tmp55 = insertelement <4 x i32> %tmp54, i32 %tmp52, i32 2
%tmp55.cast = bitcast <4 x i32> %tmp55 to <4 x float>
@@ -63,7 +63,7 @@ main_body:
IF26: ; preds = %main_body
%tmp71 = bitcast float %tmp27 to i32
- %tmp72 = insertelement <4 x i32> undef, i32 %tmp71, i32 0
+ %tmp72 = insertelement <4 x i32> poison, i32 %tmp71, i32 0
br label %LOOP
ENDIF25: ; preds = %IF29, %main_body
diff --git a/llvm/test/CodeGen/AMDGPU/unpack-half.ll b/llvm/test/CodeGen/AMDGPU/unpack-half.ll
index f1dbc7f07f595..fc3b35a6cb8bd 100644
--- a/llvm/test/CodeGen/AMDGPU/unpack-half.ll
+++ b/llvm/test/CodeGen/AMDGPU/unpack-half.ll
@@ -13,7 +13,7 @@ define amdgpu_gs void @main(i32 inreg %arg) local_unnamed_addr #0 {
%tmp = load volatile float, ptr addrspace(1) undef
%tmp1 = bitcast float %tmp to i32
%im0.i = lshr i32 %tmp1, 16
- %tmp2 = insertelement <2 x i32> undef, i32 %im0.i, i32 1
+ %tmp2 = insertelement <2 x i32> poison, i32 %im0.i, i32 1
%tmp3 = trunc <2 x i32> %tmp2 to <2 x i16>
%tmp4 = bitcast <2 x i16> %tmp3 to <2 x half>
%tmp5 = fpext <2 x half> %tmp4 to <2 x float>
diff --git a/llvm/test/CodeGen/AMDGPU/v_pack.ll b/llvm/test/CodeGen/AMDGPU/v_pack.ll
index 7b60ea100a51c..8a8829832f688 100644
--- a/llvm/test/CodeGen/AMDGPU/v_pack.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_pack.ll
@@ -130,7 +130,7 @@ define amdgpu_kernel void @v_pack_b32_v2f16(ptr addrspace(1) %in0, ptr addrspace
%v1 = load volatile half, ptr addrspace(1) %in1.gep
%v0.add = fadd half %v0, 2.0
%v1.add = fadd half %v1, 2.0
- %vec.0 = insertelement <2 x half> undef, half %v0.add, i32 0
+ %vec.0 = insertelement <2 x half> poison, half %v0.add, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half %v1.add, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
@@ -259,7 +259,7 @@ define amdgpu_kernel void @v_pack_b32_v2f16_sub(ptr addrspace(1) %in0, ptr addrs
%v1 = load volatile half, ptr addrspace(1) %in1.gep
%v0.add = fsub half %v0, 2.0
%v1.add = fadd half %v1, 2.0
- %vec.0 = insertelement <2 x half> undef, half %v0.add, i32 0
+ %vec.0 = insertelement <2 x half> poison, half %v0.add, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half %v1.add, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
@@ -504,7 +504,7 @@ define amdgpu_kernel void @v_pack_b32.fabs(ptr addrspace(1) %in0, ptr addrspace(
%v1.add = fadd half %v1, 2.0
%v0.fabs = call half @llvm.fabs.f16(half %v0.add)
%v1.fabs = call half @llvm.fabs.f16(half %v1.add)
- %vec.0 = insertelement <2 x half> undef, half %v0.fabs, i32 0
+ %vec.0 = insertelement <2 x half> poison, half %v0.fabs, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half %v1.fabs, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
@@ -635,7 +635,7 @@ define amdgpu_kernel void @v_pack_b32.fneg(ptr addrspace(1) %in0, ptr addrspace(
%v1.add = fadd half %v1, 2.0
%v0.fneg = fsub half -0.0, %v0.add
%v1.fneg = fsub half -0.0, %v1.add
- %vec.0 = insertelement <2 x half> undef, half %v0.fneg, i32 0
+ %vec.0 = insertelement <2 x half> poison, half %v0.fneg, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half %v1.fneg, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32
call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index 2d84e87722951..b81f5d0a19ba8 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -263,7 +263,7 @@ define amdgpu_kernel void @basic_smax_smin_sgpr(ptr addrspace(1) %out, i32 inreg
%src0.clamp = call i16 @llvm.smin.i16(i16 %src0.max, i16 255)
%src1.max = call i16 @llvm.smax.i16(i16 %src1, i16 0)
%src1.clamp = call i16 @llvm.smin.i16(i16 %src1.max, i16 255)
- %insert.0 = insertelement <2 x i16> undef, i16 %src0.clamp, i32 0
+ %insert.0 = insertelement <2 x i16> poison, i16 %src0.clamp, i32 0
%vec = insertelement <2 x i16> %insert.0, i16 %src1.clamp, i32 1
store <2 x i16> %vec, ptr addrspace(1) %out
ret void
@@ -362,7 +362,7 @@ define <2 x i16> @basic_smin_smax(i16 %src0, i16 %src1) {
%src0.clamp = call i16 @llvm.smax.i16(i16 %src0.min, i16 0)
%src1.min = call i16 @llvm.smin.i16(i16 %src1, i16 255)
%src1.clamp = call i16 @llvm.smax.i16(i16 %src1.min, i16 0)
- %insert.0 = insertelement <2 x i16> undef, i16 %src0.clamp, i32 0
+ %insert.0 = insertelement <2 x i16> poison, i16 %src0.clamp, i32 0
%vec = insertelement <2 x i16> %insert.0, i16 %src1.clamp, i32 1
ret <2 x i16> %vec
}
@@ -460,7 +460,7 @@ define <2 x i16> @basic_smin_smax_combined(i16 %src0, i16 %src1) {
%src0.clamp = call i16 @llvm.smax.i16(i16 %src0.min, i16 0)
%src1.max = call i16 @llvm.smax.i16(i16 %src1, i16 0)
%src1.clamp = call i16 @llvm.smin.i16(i16 %src1.max, i16 255)
- %insert.0 = insertelement <2 x i16> undef, i16 %src0.clamp, i32 0
+ %insert.0 = insertelement <2 x i16> poison, i16 %src0.clamp, i32 0
%vec = insertelement <2 x i16> %insert.0, i16 %src1.clamp, i32 1
ret <2 x i16> %vec
}
@@ -1066,7 +1066,7 @@ define i16 @basic_smax_smin_vec_cast(i16 %src0, i16 %src1) {
%src0.clamp = call i16 @llvm.smin.i16(i16 %src0.max, i16 255)
%src1.max = call i16 @llvm.smax.i16(i16 %src1, i16 0)
%src1.clamp = call i16 @llvm.smin.i16(i16 %src1.max, i16 255)
- %insert.0 = insertelement <2 x i16> undef, i16 %src0.clamp, i32 0
+ %insert.0 = insertelement <2 x i16> poison, i16 %src0.clamp, i32 0
%vec = insertelement <2 x i16> %insert.0, i16 %src1.clamp, i32 1
%vec.trunc = trunc <2 x i16> %vec to <2 x i8>
%cast = bitcast <2 x i8> %vec.trunc to i16
diff --git a/llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll b/llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
index e2ba9d0c087ad..1daba85ae0122 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
@@ -11,7 +11,7 @@ define amdgpu_kernel void @spam(ptr addrspace(1) noalias %arg) {
%tmp2 = getelementptr inbounds double, ptr addrspace(1) %arg, i64 %tmp1
%tmp3 = load double, ptr addrspace(1) %tmp2, align 8
%tmp4 = fadd double undef, 0.000000e+00
- %tmp5 = insertelement <2 x double> undef, double %tmp4, i64 0
+ %tmp5 = insertelement <2 x double> poison, double %tmp4, i64 0
%tmp6 = insertelement <2 x double> %tmp5, double %tmp3, i64 1
%tmp7 = insertelement <2 x double> %tmp6, double 0.000000e+00, i64 1
%tmp8 = fadd <2 x double> zeroinitializer, undef
diff --git a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
index e9ae1ebe4572b..0ab09354ec06b 100644
--- a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
@@ -2383,7 +2383,7 @@ define <2 x i16> @v2i16_hi16bits(ptr addrspace(1) %x0) {
; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%load0 = load <2 x i16>, ptr addrspace(1) %x0, align 4
- %insert1 = insertelement <2 x i16> undef, i16 0, i32 0
+ %insert1 = insertelement <2 x i16> poison, i16 0, i32 0
%insert2 = insertelement <2 x i16> %insert1, i16 0, i32 1
%vec.ret = shufflevector <2 x i16> %insert2, <2 x i16> %load0, <2 x i32> <i32 0, i32 3>
ret <2 x i16> %vec.ret
@@ -2415,7 +2415,7 @@ define <2 x half> @v2half_hi16bits(ptr addrspace(1) %x0) {
; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%load0 = load <2 x half>, ptr addrspace(1) %x0, align 4
- %insert1 = insertelement <2 x half> undef, half 0.0, i32 0
+ %insert1 = insertelement <2 x half> poison, half 0.0, i32 0
%insert2 = insertelement <2 x half> %insert1, half 0.0, i32 1
%vec.ret = shufflevector <2 x half> %insert2, <2 x half> %load0, <2 x i32> <i32 0, i32 3>
ret <2 x half> %vec.ret
@@ -5330,7 +5330,7 @@ define <2 x bfloat> @v2bfloat_hi16bits(ptr addrspace(1) %x0) {
; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%load0 = load <2 x bfloat>, ptr addrspace(1) %x0, align 4
- %insert1 = insertelement <2 x bfloat> undef, bfloat 0.0, i32 0
+ %insert1 = insertelement <2 x bfloat> poison, bfloat 0.0, i32 0
%insert2 = insertelement <2 x bfloat> %insert1, bfloat 0.0, i32 1
%vec.ret = shufflevector <2 x bfloat> %insert2, <2 x bfloat> %load0, <2 x i32> <i32 0, i32 3>
ret <2 x bfloat> %vec.ret
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll b/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
index 65a7554bb66a5..a69ada244ded9 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
@@ -347,7 +347,7 @@ bb145: ; preds = %bb12
%tmp147 = bitcast float %tmp95 to i32
%tmp148 = add i32 %tmp11, %tmp147
%tmp149 = bitcast i32 %tmp148 to float
- %tmp150 = insertelement <128 x float> undef, float %tmp91, i32 0
+ %tmp150 = insertelement <128 x float> poison, float %tmp91, i32 0
%tmp151 = insertelement <128 x float> %tmp150, float %tmp90, i32 1
%tmp152 = insertelement <128 x float> %tmp151, float %tmp89, i32 2
%tmp153 = insertelement <128 x float> %tmp152, float %tmp87, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll b/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
index 0cabfa9aea0e4..8dfd841671730 100644
--- a/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
+++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
@@ -220,7 +220,7 @@ bb157: ; preds = %bb24
%tmp159 = bitcast float %tmp107 to i32
%tmp160 = add i32 %tmp23, %tmp159
%tmp161 = bitcast i32 %tmp160 to float
- %tmp162 = insertelement <128 x float> undef, float %tmp103, i32 0
+ %tmp162 = insertelement <128 x float> poison, float %tmp103, i32 0
%tmp163 = insertelement <128 x float> %tmp162, float %tmp102, i32 1
%tmp164 = insertelement <128 x float> %tmp163, float %tmp101, i32 2
%tmp165 = insertelement <128 x float> %tmp164, float %tmp99, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll b/llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
index 186f50480a34d..26be45e45697f 100644
--- a/llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
+++ b/llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
@@ -14,10 +14,10 @@ bb:
%tmp = extractelement <4 x double> %arg, i64 0
%tmp1 = fcmp uno double %tmp, 0.000000e+00
%tmp2 = sext i1 %tmp1 to i64
- %tmp3 = insertelement <4 x i64> undef, i64 %tmp2, i32 0
- %tmp4 = insertelement <4 x i64> %tmp3, i64 undef, i32 1
- %tmp5 = insertelement <4 x i64> %tmp4, i64 undef, i32 2
- %tmp6 = insertelement <4 x i64> %tmp5, i64 undef, i32 3
+ %tmp3 = insertelement <4 x i64> poison, i64 %tmp2, i32 0
+ %tmp4 = insertelement <4 x i64> %tmp3, i64 poison, i32 1
+ %tmp5 = insertelement <4 x i64> %tmp4, i64 poison, i32 2
+ %tmp6 = insertelement <4 x i64> %tmp5, i64 poison, i32 3
%tmp7 = fcmp une <4 x double> %arg, zeroinitializer
%tmp8 = icmp sgt <4 x i64> %tmp6, <i64 -1, i64 -1, i64 -1, i64 -1>
%tmp9 = and <4 x i1> %tmp8, %tmp7
@@ -36,10 +36,10 @@ bb:
%tmp = extractelement <4 x i64> %arg, i64 0
%tmp1 = icmp eq i64 %tmp, 0
%tmp2 = sext i1 %tmp1 to i64
- %tmp3 = insertelement <4 x i64> undef, i64 %tmp2, i32 0
- %tmp4 = insertelement <4 x i64> %tmp3, i64 undef, i32 1
- %tmp5 = insertelement <4 x i64> %tmp4, i64 undef, i32 2
- %tmp6 = insertelement <4 x i64> %tmp5, i64 undef, i32 3
+ %tmp3 = insertelement <4 x i64> poison, i64 %tmp2, i32 0
+ %tmp4 = insertelement <4 x i64> %tmp3, i64 poison, i32 1
+ %tmp5 = insertelement <4 x i64> %tmp4, i64 poison, i32 2
+ %tmp6 = insertelement <4 x i64> %tmp5, i64 poison, i32 3
%tmp7 = icmp ne <4 x i64> %arg, zeroinitializer
%tmp8 = icmp sgt <4 x i64> %tmp6, <i64 -1, i64 -1, i64 -1, i64 -1>
%tmp9 = and <4 x i1> %tmp8, %tmp7
diff --git a/llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll b/llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll
index e68f232a9f506..82d276e758c7b 100644
--- a/llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll
+++ b/llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll
@@ -21,7 +21,7 @@ main_body:
%a = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %attr) #1
%b = call float @llvm.amdgcn.lds.param.load(i32 1, i32 0, i32 %attr) #1
%c = call float @llvm.amdgcn.lds.param.load(i32 2, i32 0, i32 %attr) #1
- %tmp_0 = insertelement <3 x float> undef, float %a, i32 0
+ %tmp_0 = insertelement <3 x float> poison, float %a, i32 0
%tmp_1 = insertelement <3 x float> %tmp_0, float %b, i32 1
%tmp_2 = insertelement <3 x float> %tmp_1, float %c, i32 2
%res = fadd <3 x float> %tmp_2, %to_add
@@ -50,7 +50,7 @@ main_body:
%a = call float @llvm.amdgcn.lds.direct.load(i32 %arg_0) #1
%b = call float @llvm.amdgcn.lds.direct.load(i32 %arg_1) #1
%c = call float @llvm.amdgcn.lds.direct.load(i32 %arg_2) #1
- %tmp_0 = insertelement <3 x float> undef, float %a, i32 0
+ %tmp_0 = insertelement <3 x float> poison, float %a, i32 0
%tmp_1 = insertelement <3 x float> %tmp_0, float %b, i32 1
%tmp_2 = insertelement <3 x float> %tmp_1, float %c, i32 2
%res = fadd <3 x float> %tmp_2, %to_add
diff --git a/llvm/test/CodeGen/AMDGPU/xor3.ll b/llvm/test/CodeGen/AMDGPU/xor3.ll
index 864dec3563a6b..6c5a4670b245e 100644
--- a/llvm/test/CodeGen/AMDGPU/xor3.ll
+++ b/llvm/test/CodeGen/AMDGPU/xor3.ll
@@ -108,7 +108,7 @@ define amdgpu_ps <2 x float> @xor3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x
%inner = xor i32 %a, %b
%outer = xor i32 %inner, %c
%x1 = mul i32 %outer, %x
- %r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
+ %r1 = insertelement <2 x i32> poison, i32 %outer, i32 0
%r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
%bc = bitcast <2 x i32> %r0 to <2 x float>
ret <2 x float> %bc
@@ -128,7 +128,7 @@ define amdgpu_ps <2 x float> @xor3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
; GFX10-NEXT: ; return to shader part epilog
%inner = xor i32 %a, %b
%outer = xor i32 %inner, %c
- %r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
+ %r1 = insertelement <2 x i32> poison, i32 %inner, i32 0
%r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
%bc = bitcast <2 x i32> %r0 to <2 x float>
ret <2 x float> %bc
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