[llvm] [RISCV][MC] Correct the register state update for auipc (PR #130897)

[via llvm-commits]

https://github.com/liulin92 created https://github.com/llvm/llvm-project/pull/130897

AUIPC is a 20-bits value which is used to form 32-bits offset thus it should be a int32 value, then signed-extend to int64.

>From d727428ebf82f0d12d9cec4ba6e7ee21cc60926f Mon Sep 17 00:00:00 2001
From: liulin92 <lindanliulin at gmail.com>
Date: Wed, 12 Mar 2025 11:20:56 +0800
Subject: [PATCH] [RISCV][MC] Correct the register state update for auipc

AUIPC is a 20-bits value which is used to form 32-bits
offset thus it should be a int32 value, then signed-extend
to int64.
---
 llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 2 +-
 llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s        | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 5f1d7b03f3218..4fff214f7b61d 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -195,7 +195,7 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
     }
     case RISCV::AUIPC:
       setGPRState(Inst.getOperand(0).getReg(),
-                  Addr + (Inst.getOperand(1).getImm() << 12));
+                  Addr + ((int32_t)Inst.getOperand(1).getImm() << 12));
       break;
     }
   }
diff --git a/llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s b/llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s
index 2be42ad1c1164..93dd4cc4bac92 100644
--- a/llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s
+++ b/llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s
@@ -78,3 +78,8 @@ nop
 bar:
 # CHECK: 60: c.nop
 nop
+
+# CHECK-LABEL: 00011000 <far>:
+.org 0x11000
+# CHECK: jalr ra, 0x0(ra) <foo>
+call foo