[llvm] [RISCV] Add an error that Xqciac and Xqcicm are not compatible with C+D or Zcd. (PR #130816)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/130816

I was reviewing encodings to put the disassembling of vendor instructions after after standard instructions and found that these overlap with c.fldsp and c.fsdsp.

>From 6ee708badffa6d9001b7919a6addd6a015d679b4 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 11 Mar 2025 12:14:30 -0700
Subject: [PATCH] [RISCV] Add an error that Xqciac and Xqcicm are not
 compatible with C+D or Zcd.

I was reviewing encodings to put the disassembling of vendor instructions
after after standard instructions and found that these overlap with
c.fldsp and c.fsdsp.
---
 llvm/lib/TargetParser/RISCVISAInfo.cpp        | 21 +++++++++-------
 .../TargetParser/RISCVISAInfoTest.cpp         | 24 +++++++++++++++++++
 2 files changed, 37 insertions(+), 8 deletions(-)

diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index dd74f79f04b92..4276e94ec9b3e 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -740,13 +740,16 @@ Error RISCVISAInfo::checkDependency() {
   bool HasZfinx = Exts.count("zfinx") != 0;
   bool HasVector = Exts.count("zve32x") != 0;
   bool HasZvl = MinVLen != 0;
-  bool HasZcmt = Exts.count("zcmt") != 0;
+  bool HasZcmp = Exts.count("zcmp") != 0;
+  bool HasXqccmp = Exts.count("xqccmp") != 0;
+
   static constexpr StringLiteral XqciExts[] = {
       {"xqcia"},   {"xqciac"}, {"xqcibm"},  {"xqcicli"},
       {"xqcicm"},  {"xqcics"}, {"xqcicsr"}, {"xqciint"},
       {"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
-  bool HasZcmp = Exts.count("zcmp") != 0;
-  bool HasXqccmp = Exts.count("xqccmp") != 0;
+  static constexpr StringLiteral ZcdOverlaps[] = {
+    {"zcmt"}, {"zcmp"}, {"xqciac"}, {"xqcicm"}
+  };
 
   if (HasI && HasE)
     return getIncompatibleError("i", "e");
@@ -757,11 +760,13 @@ Error RISCVISAInfo::checkDependency() {
   if (HasZvl && !HasVector)
     return getExtensionRequiresError("zvl*b", "v' or 'zve*");
 
-  if ((HasZcmt || Exts.count("zcmp")) && HasD && (HasC || Exts.count("zcd")))
-    return getError(Twine("'") + (HasZcmt ? "zcmt" : "zcmp") +
-                    "' extension is incompatible with '" +
-                    (HasC ? "c" : "zcd") +
-                    "' extension when 'd' extension is enabled");
+  if (HasD && (HasC || Exts.count("zcd")))
+    for (auto Ext : ZcdOverlaps)
+      if (Exts.count(Ext.str()))
+        return getError(Twine("'") + Ext +
+                        "' extension is incompatible with '" +
+                        (HasC ? "c" : "zcd") +
+                        "' extension when 'd' extension is enabled");
 
   if (XLen != 32 && Exts.count("zcf"))
     return getError("'zcf' is only supported for 'rv32'");
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index e24b2d47f6bc4..c86108193fd9a 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -663,6 +663,30 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
         ::testing::EndsWith(" is only supported for 'rv32'"));
   }
 
+  for (StringRef Input : {"rv32idc_xqciac0p3"}) {
+    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+              "'xqciac' extension is incompatible with 'c' extension when 'd' "
+              "extension is enabled");
+  }
+
+  for (StringRef Input : {"rv32i_zcd_xqciac0p3"}) {
+    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+              "'xqciac' extension is incompatible with 'zcd' extension when 'd' "
+              "extension is enabled");
+  }
+
+  for (StringRef Input : {"rv32idc_xqcicm0p2"}) {
+    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+              "'xqcicm' extension is incompatible with 'c' extension when 'd' "
+              "extension is enabled");
+  }
+
+  for (StringRef Input : {"rv32i_zcd_xqcicm0p2"}) {
+    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+              "'xqcicm' extension is incompatible with 'zcd' extension when 'd' "
+              "extension is enabled");
+  }
+
   for (StringRef Input : {"rv32i_zcmp_xqccmp0p1", "rv64i_zcmp_xqccmp0p1"}) {
     EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
               "'zcmp' and 'xqccmp' extensions are incompatible");