[llvm] [AMDGPU] Ignore RegMask operands when folding operands to SALU insts (PR #130813)

[Mirko Brkušanin via llvm-commits]

https://github.com/mbrkusanin created https://github.com/llvm/llvm-project/pull/130813

Otherwise we hit an assert in isInlineConstant.

>From 2fae79d2bf673fb9a5b3e8d6aef20692092d6918 Mon Sep 17 00:00:00 2001
From: Mirko Brkusanin <Mirko.Brkusanin at amd.com>
Date: Tue, 11 Mar 2025 19:20:48 +0100
Subject: [PATCH] [AMDGPU] Ignore RegMask operands when folding operands to
 SALU insts

---
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp           |  2 +-
 llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir | 15 +++++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index ae285d069d876..1e025f481ffa9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6067,7 +6067,7 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
       if (i == OpIdx)
         continue;
       const MachineOperand &Op = MI.getOperand(i);
-      if (!Op.isReg() && !Op.isFI() &&
+      if (!Op.isReg() && !Op.isFI() && !Op.isRegMask() &&
           !isInlineConstant(Op, InstDesc.operands()[i]) &&
           !Op.isIdenticalTo(*MO))
         return false;
diff --git a/llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir b/llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir
index d85d77e338870..cc4314263bcba 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir
@@ -268,3 +268,18 @@ body: |
     %0:sreg_32 = S_MOV_B32 80
     S_CMP_EQ_U32 %0, 64, implicit-def $scc
 ...
+
+# Ignore regmask operands
+# GCN-LABEL: name: test_si_cs_chain_fold_with_regmask{{$}}
+# GCN: SI_CS_CHAIN_TC_W32 %0, 0, 0, 1234, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8
+---
+name: test_si_cs_chain_fold_with_regmask
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr2_sgpr3, $vgpr8
+
+    %1:ccr_sgpr_64 = COPY $sgpr2_sgpr3
+    %2:sreg_32 = S_MOV_B32 1234
+    SI_CS_CHAIN_TC_W32 %1:ccr_sgpr_64, 0, 0, %2:sreg_32, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8
+...