[llvm] 2bf7018 - [RISCV] Move let statement for hasSideEffects, mayLoad, mayStore into BranchCC_rri. NFC (#130721)

[via llvm-commits]

Author: Craig Topper
Date: 2025-03-11T09:24:13-07:00
New Revision: 2bf7018bb03eb93b56ad86caac40ced8b5c6744b

URL: https://github.com/llvm/llvm-project/commit/2bf7018bb03eb93b56ad86caac40ced8b5c6744b
DIFF: https://github.com/llvm/llvm-project/commit/2bf7018bb03eb93b56ad86caac40ced8b5c6744b.diff

LOG: [RISCV] Move let statement for hasSideEffects, mayLoad, mayStore into BranchCC_rri. NFC (#130721)

This is consistent with the isBranch and isTerminator flags already in
the class.

Addresses feedback given on #130714 where I copied the inconsistent
split into RISCVInstrInfoXCV.td.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 5ce826b136832..aab368680e814 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -523,7 +523,6 @@ include "RISCVInstrFormats.td"
 // Instruction Class Templates
 //===----------------------------------------------------------------------===//
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class BranchCC_rri<bits<3> funct3, string opcodestr>
     : RVInstB<funct3, OPC_BRANCH, (outs),
               (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
@@ -531,6 +530,9 @@ class BranchCC_rri<bits<3> funct3, string opcodestr>
       Sched<[WriteJmp, ReadJmp, ReadJmp]> {
   let isBranch = 1;
   let isTerminator = 1;
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 0;
 }
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {