[llvm] [SPIR-V] Add `OpConstantCompositeContinuedINTEL` instruction (PR #129086)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 11 09:06:32 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-spir-v
Author: Viktoria Maximova (vmaksimo)
<details>
<summary>Changes</summary>
Specification:
https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_long_composites.html
---
Patch is 725.72 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/129086.diff
6 Files Affected:
- (modified) llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp (+19-13)
- (modified) llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp (+7-2)
- (modified) llvm/lib/Target/SPIRV/SPIRVUtils.cpp (+11-4)
- (modified) llvm/lib/Target/SPIRV/SPIRVUtils.h (+5-4)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-constant-array.ll (+28)
- (added) llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-constant-composite.ll (+27)
``````````diff
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index b188f36ca9a9e..6e0349a463aad 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2940,24 +2940,30 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
case Intrinsic::spv_const_composite: {
// If no values are attached, the composite is null constant.
bool IsNull = I.getNumExplicitDefs() + 1 == I.getNumExplicitOperands();
- // Select a proper instruction.
- unsigned Opcode = SPIRV::OpConstantNull;
SmallVector<Register> CompositeArgs;
- if (!IsNull) {
- Opcode = SPIRV::OpConstantComposite;
- if (!wrapIntoSpecConstantOp(I, CompositeArgs))
- return false;
- }
MRI->setRegClass(ResVReg, GR.getRegClass(ResType));
- auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType));
+
// skip type MD node we already used when generated assign.type for this
if (!IsNull) {
- for (Register OpReg : CompositeArgs)
- MIB.addUse(OpReg);
+ if (!wrapIntoSpecConstantOp(I, CompositeArgs))
+ return false;
+ MachineIRBuilder MIR(I);
+ SmallVector<MachineInstr *, 4> Instructions = createContinuedInstructions(
+ MIR, SPIRV::OpConstantComposite, 3,
+ SPIRV::OpConstantCompositeContinuedINTEL, CompositeArgs, ResVReg,
+ GR.getSPIRVTypeID(ResType));
+ for (auto *Instr : Instructions) {
+ Instr->setDebugLoc(I.getDebugLoc());
+ if (!constrainSelectedInstRegOperands(*Instr, TII, TRI, RBI))
+ return false;
+ }
+ return true;
+ } else {
+ auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(ResType));
+ return MIB.constrainAllUses(TII, TRI, RBI);
}
- return MIB.constrainAllUses(TII, TRI, RBI);
}
case Intrinsic::spv_assign_name: {
auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpName));
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index e0b348f0bba10..e45d517c933ab 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -361,11 +361,16 @@ void SPIRVModuleAnalysis::visitDecl(
} else if (Opcode == SPIRV::OpFunction ||
Opcode == SPIRV::OpFunctionParameter) {
GReg = handleFunctionOrParameter(MF, MI, GlobalToGReg, IsFunDef);
- } else if (Opcode == SPIRV::OpTypeStruct) {
+ } else if (Opcode == SPIRV::OpTypeStruct ||
+ Opcode == SPIRV::OpConstantComposite) {
GReg = handleTypeDeclOrConstant(MI, SignatureToGReg);
const MachineInstr *NextInstr = MI.getNextNode();
while (NextInstr &&
- NextInstr->getOpcode() == SPIRV::OpTypeStructContinuedINTEL) {
+ ((Opcode == SPIRV::OpTypeStruct &&
+ NextInstr->getOpcode() == SPIRV::OpTypeStructContinuedINTEL) ||
+ (Opcode == SPIRV::OpConstantComposite &&
+ NextInstr->getOpcode() ==
+ SPIRV::OpConstantCompositeContinuedINTEL))) {
MCRegister Tmp = handleTypeDeclOrConstant(*NextInstr, SignatureToGReg);
MAI.setRegisterAlias(MF, NextInstr->getOperand(0).getReg(), Tmp);
MAI.setSkipEmission(NextInstr);
diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
index ce4f6d6c9288f..6edc757a88d37 100644
--- a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp
@@ -813,10 +813,13 @@ bool isSpvIntrinsic(const Value *Arg) {
// Function to create continued instructions for SPV_INTEL_long_composites
// extension
-void createContinuedInstructions(MachineIRBuilder &MIRBuilder, unsigned Opcode,
- unsigned MinWC, unsigned ContinuedOpcode,
- ArrayRef<Register> Args,
- Register ReturnRegister, Register TypeID) {
+SmallVector<MachineInstr *, 4>
+createContinuedInstructions(MachineIRBuilder &MIRBuilder, unsigned Opcode,
+ unsigned MinWC, unsigned ContinuedOpcode,
+ ArrayRef<Register> Args, Register ReturnRegister,
+ Register TypeID) {
+
+ SmallVector<MachineInstr *, 4> Instructions;
constexpr unsigned MaxWordCount = UINT16_MAX;
const size_t NumElements = Args.size();
size_t MaxNumElements = MaxWordCount - MinWC;
@@ -835,12 +838,16 @@ void createContinuedInstructions(MachineIRBuilder &MIRBuilder, unsigned Opcode,
for (size_t I = 0; I < SPIRVStructNumElements; ++I)
MIB.addUse(Args[I]);
+ Instructions.push_back(MIB.getInstr());
+
for (size_t I = SPIRVStructNumElements; I < NumElements;
I += MaxNumElements) {
auto MIB = MIRBuilder.buildInstr(ContinuedOpcode);
for (size_t J = I; J < std::min(I + MaxNumElements, NumElements); ++J)
MIB.addUse(Args[J]);
+ Instructions.push_back(MIB.getInstr());
}
+ return Instructions;
}
} // namespace llvm
diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.h b/llvm/lib/Target/SPIRV/SPIRVUtils.h
index 180d3a29d170f..9100e6fbf39cc 100644
--- a/llvm/lib/Target/SPIRV/SPIRVUtils.h
+++ b/llvm/lib/Target/SPIRV/SPIRVUtils.h
@@ -454,10 +454,11 @@ inline FPDecorationId demangledPostfixToDecorationId(const std::string &S) {
return It == Mapping.end() ? FPDecorationId::NONE : It->second;
}
-void createContinuedInstructions(MachineIRBuilder &MIRBuilder, unsigned Opcode,
- unsigned MinWC, unsigned ContinuedOpcode,
- ArrayRef<Register> Args,
- Register ReturnRegister, Register TypeID);
+SmallVector<MachineInstr *, 4>
+createContinuedInstructions(MachineIRBuilder &MIRBuilder, unsigned Opcode,
+ unsigned MinWC, unsigned ContinuedOpcode,
+ ArrayRef<Register> Args, Register ReturnRegister,
+ Register TypeID);
} // namespace llvm
#endif // LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-constant-array.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-constant-array.ll
new file mode 100644
index 0000000000000..b197820336387
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_long_composites/long-constant-array.ll
@@ -0,0 +1,28 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_long_composites %s -o %t.spt
+; RUN: FileCheck %s --input-file %t.spt
+
+; TODO: enable back once spirv-val knows about OpTypeStructContinuedINTEL type and OpConstantCompositeContinuedINTEL instruction
+; RUNx: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_long_composites %s -o - -filetype=obj | spirv-val %}
+
+; CHECK: OpCapability LongCompositesINTEL
+; CHECK: OpExtension "SPV_INTEL_long_composites"
+; CHECK: OpName %[[#VarName:]] "big_array"
+; CHECK-DAG: %[[#TInt:]] = OpTypeInt 8
+; CHECK-DAG: %[[#TInt32:]] = OpTypeInt 32
+
+; CHECK: %[[#ArrSize:]] = OpConstant %[[#]] 78000
+; CHECK: %[[#TArr:]] = OpTypeArray %[[#TInt]] %[[#ArrSize]]
+
+; CHECK: %[[#Constant:]] = OpConstantComposite %[[#TArr]]
+; CHECK-NEXT: OpConstantCompositeContinuedINTEL
+; CHECK: %[[#VarName]] = OpVariable %[[#]] UniformConstant %[[#Constant]]
+
+; To be sure we generate this instruction only once
+; CHECK-NOT: OpConstantCompositeContinuedINTEL
+
+ at big_array = local_unnamed_addr addrspace(2) constant [78000 x i8] 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[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/129086
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