[llvm] [AMDGPU][True16][CodeGen] minmax pattern only for GFX11+ (PR #130786)

[Brox Chen via llvm-commits]

https://github.com/broxigarchen created https://github.com/llvm/llvm-project/pull/130786

Fixed a small error codegen, move minmax pattern to GFX11+ only

>From d0fcfe40803f127bede14dd9630d45cdd96595f6 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Tue, 11 Mar 2025 11:51:00 -0400
Subject: [PATCH] quick fix for minmax pattern

---
 llvm/lib/Target/AMDGPU/SIInstructions.td | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 985337da1909d..aabbd91e69589 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3949,7 +3949,6 @@ def : FPMinMaxPat<V_MINMAX_F32_e64, f32, fmaxnum_like, fminnum_like_oneuse>;
 def : FPMinMaxPat<V_MAXMIN_F32_e64, f32, fminnum_like, fmaxnum_like_oneuse>;
 def : FPMinCanonMaxPat<V_MINMAX_F32_e64, f32, fmaxnum_like, fminnum_like_oneuse>;
 def : FPMinCanonMaxPat<V_MAXMIN_F32_e64, f32, fminnum_like, fmaxnum_like_oneuse>;
-}
 
 let True16Predicate = UseRealTrue16Insts in {
 def : FPMinMaxPat<V_MINMAX_F16_t16_e64, f16, fmaxnum_like, fminnum_like_oneuse>;
@@ -3965,6 +3964,8 @@ def : FPMinCanonMaxPat<V_MINMAX_F16_fake16_e64, f16, fmaxnum_like, fminnum_like_
 def : FPMinCanonMaxPat<V_MAXMIN_F16_fake16_e64, f16, fminnum_like, fmaxnum_like_oneuse>;
 }
 
+} // End OtherPredicates = [isGFX11Plus]
+
 let SubtargetPredicate = isGFX9Plus in {
 let True16Predicate = NotHasTrue16BitInsts in {
   defm : Int16Med3Pat<V_MED3_I16_e64, smin, smax, VSrc_b16>;