[llvm] [AMDGPU] Search for literals among explicit operands only (PR #130771)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Diana Picus (rovka)

<details>
<summary>Changes</summary>

The code in SIInstrInfo::isOperandLegal crashes in some rare cases when dealing with call pseudos, which are variadic and may thus have more operands than those listed in their instruction descriptions. The excess operands will usually be implicit registers, but may also be the call preserved reg mask.

This patch attempts to fix the issue by iterating only through the explicit operands while searching for literal operands.

---
Full diff: https://github.com/llvm/llvm-project/pull/130771.diff


1 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index ae285d069d876..da8533fd5ef5d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6063,7 +6063,7 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
     }
   } else if (!IsInlineConst && !MO->isReg() && isSALU(MI)) {
     // There can be at most one literal operand, but it can be repeated.
-    for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
+    for (unsigned i = 0, e = MI.getNumExplicitOperands(); i != e; ++i) {
       if (i == OpIdx)
         continue;
       const MachineOperand &Op = MI.getOperand(i);

``````````

</details>


https://github.com/llvm/llvm-project/pull/130771