[llvm] [AMDGPU][True16][CodeGen] update waitcnt for true16 (PR #128927)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 11 03:56:35 PDT 2025
================
@@ -748,27 +748,32 @@ RegInterval WaitcntBrackets::getRegInterval(const MachineInstr *MI,
RegInterval Result;
- unsigned Reg = TRI->getEncodingValue(AMDGPU::getMCReg(Op.getReg(), *ST)) &
- AMDGPU::HWEncoding::REG_IDX_MASK;
+ MCRegister MCReg = AMDGPU::getMCReg(Op.getReg(), *ST);
+ unsigned RegIdx = TRI->getHWRegIndex(MCReg);
+ assert(isUInt<8>(RegIdx));
+ const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Op.getReg());
+ unsigned Size = TRI->getRegSizeInBits(*RC);
+
+ // AGPRs/VGPRs are tracked every 16 bits, SGPRs by 32 bits
if (TRI->isVectorRegister(*MRI, Op.getReg())) {
- assert(Reg <= SQ_MAX_PGM_VGPRS);
+ unsigned Reg = (RegIdx << 1) | (AMDGPU::isHi16Reg(MCReg, *TRI) ? 1 : 0);
+ assert(Reg <= AGPR_OFFSET);
----------------
jayfoad wrote:
```suggestion
unsigned Reg = RegIdx << 1 | (AMDGPU::isHi16Reg(MCReg, *TRI) ? 1 : 0);
assert(Reg < AGPR_OFFSET);
```
https://github.com/llvm/llvm-project/pull/128927
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