[llvm] [InstCombine] Fold fneg/fabs patterns with ppc_f128 (PR #130557)

[Nikita Popov via llvm-commits]

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@@ -144,9 +147,15 @@ static constexpr fltSemantics semFloat8E4M3B11FNUZ = {
     4, -10, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::NegativeZero};
 static constexpr fltSemantics semFloat8E3M4 = {3, -2, 5, 8};
 static constexpr fltSemantics semFloatTF32 = {127, -126, 11, 19};
-static constexpr fltSemantics semFloat8E8M0FNU = {
-    127,   -127, 1, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::AllOnes,
-    false, false};
+static constexpr fltSemantics semFloat8E8M0FNU = {127,
+                                                  -127,
+                                                  1,
+                                                  8,
+                                                  fltNonfiniteBehavior::NanOnly,
+                                                  fltNanEncoding::AllOnes,
+                                                  false,
+                                                  false,
+                                                  false};
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nikic wrote:

Why is this one false? The doc comment says:
```
    // 8-bit floating point number mostly following IEEE-754 conventions
    // and bit layout S1E5M2 described in https://arxiv.org/abs/2206.02915,
    // with expanded range and with no infinity or signed zero.
    // NaN is represented as negative zero. (FN -> Finite, UZ -> unsigned zero).
    // This format's exponent bias is 16, instead of the 15 (2 ** (5 - 1) - 1)
    // that IEEE precedent would imply.
```
So it does have a sign bit, I think? Or is the concern that negative zero is NaN?

https://github.com/llvm/llvm-project/pull/130557