[llvm] [RISCV] Sink hasSideEffects, mayLoad, mayStore from defs to classes in RISCVInstrInfo.td. NFC (PR #130714)

[Craig Topper via llvm-commits]

================
@@ -495,16 +490,18 @@ let Predicates = [HasVendorXCVsimd, IsRV32],
   def CV_SUB_DIV8 :    CVSIMDRR<0b01110, 1, 0, 0b110, "cv.sub.div8">;
 }
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class CVInstImmBranch<bits<3> funct3, dag outs, dag ins,
                       string opcodestr, string argstr>
     : RVInstB<funct3, OPC_CUSTOM_0, outs, ins, opcodestr, argstr> {
   bits<5> imm5;
   let rs2 = imm5;
+  let isBranch = 1;
+  let isTerminator = 1;
----------------
topperc wrote:

I did it this way because that's how we did it in RISCVInstrInfo.td so I was being consistent. I can change it though.

```
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in                             
class BranchCC_rri<bits<3> funct3, string opcodestr>                             
    : RVInstB<funct3, OPC_BRANCH, (outs),                                        
              (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),                      
              opcodestr, "$rs1, $rs2, $imm12">,                                  
      Sched<[WriteJmp, ReadJmp, ReadJmp]> {                                      
  let isBranch = 1;                                                              
  let isTerminator = 1;                                                          
} 
```

https://github.com/llvm/llvm-project/pull/130714