[llvm] [AMDGPU] Narrow 64 bit math to 32 bit if profitable (PR #130577)

[Yingwei Zheng via llvm-commits]

dtcxzyw wrote:

> > > > How about sext operations with sign bit is 1?
> > > 
> > > 
> > > Hi @shiltian , there may be problem with sext if I'm not wrong, using the following example:
> > > ```
> > > define i64 @narrow_add(i64 noundef %a, i64 noundef %b) {
> > >   %zext0 = and i64 %a, 1073741824 ; 0x0000000040000000
> > >   %zext1 = and i64 %b, 1073741824 ; 0x0000000040000000
> > >   %add = add i64 %zext0, %zext1
> > >   ret i64 %add
> > > }
> > > ```
> > > 
> > > 
> > >     
> > >       
> > >     
> > > 
> > >       
> > >     
> > > 
> > >     
> > >   
> > > So `%zext0` and `%zext1` either going to equal to 0x0000000040000000 or 0 in 64 bit .
> > > When `%zext0`=`%zext2`=0x40000000 then `%zext0 + %zext2 = 0x0000000080000000`
> > > If I truncate both `%zext0` and `%zext1` into 32bit, then I have 0x40000000 and truncated add for 32 bit is 0x80000000
> > > The 31'th bit is 1, with sext this will extend to 0xFFFFFFFF80000000, which is not equals to `%zext0 + %zext2`
> > 
> > 
> > You should check whether both LHS and RHS have more than 33 sign bits.
> 
> Hi @dtcxzyw I think because the const that is getting check is the second operand of and, so even if I have the following:
> 
> ```
> define i64 @narrow_add(i64 noundef %a, i64 noundef %b) {
>   %zext0 = and i64 %a, 0xFFFFFFFFA0000000 ; all upper 33 bits are 1
>   %zext1 = and i64 %b, 0xFFFFFFFFA0000000
>   %add = add i64 %zext0, %zext1
>   ret i64 %add
> }
> ```
> 
> It could also be true that `%zext0`=`%zext2`=0x40000000...... which still causing the same problem with sext..

https://alive2.llvm.org/ce/z/Bom92i Having 34 sign bits should work.


https://github.com/llvm/llvm-project/pull/130577