[llvm] b9cb931 - [X86] combineConcatVectorOps - convert X86ISD::VPERMV3 concatenation to use combineConcatVectorOps recursion
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 10 11:53:25 PDT 2025
Author: Simon Pilgrim
Date: 2025-03-10T18:52:59Z
New Revision: b9cb931713ed3f05568e8a091bd47a3e865f059f
URL: https://github.com/llvm/llvm-project/commit/b9cb931713ed3f05568e8a091bd47a3e865f059f
DIFF: https://github.com/llvm/llvm-project/commit/b9cb931713ed3f05568e8a091bd47a3e865f059f.diff
LOG: [X86] combineConcatVectorOps - convert X86ISD::VPERMV3 concatenation to use combineConcatVectorOps recursion
Only concatenate X86ISD::VPERMV3 nodes if at least one operand is beneficial to concatenate
Also add missing useAVX512Regs check
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index aec071f038dc6..1bda187810a63 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -58106,6 +58106,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
}
break;
case X86ISD::VPERMV:
+ // TODO: Handle 256-bit and NumOps == 4 cases.
if (!IsSplat && NumOps == 2 &&
(VT.is512BitVector() && Subtarget.useAVX512Regs())) {
MVT OpVT = Op0.getSimpleValueType();
@@ -58131,7 +58132,9 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
}
break;
case X86ISD::VPERMV3:
- if (!IsSplat && NumOps == 2 && VT.is512BitVector()) {
+ // TODO: Handle 256-bit and NumOps == 4 cases.
+ if (!IsSplat && NumOps == 2 &&
+ (VT.is512BitVector() && Subtarget.useAVX512Regs())) {
MVT OpVT = Op0.getSimpleValueType();
int NumSrcElts = OpVT.getVectorNumElements();
SmallVector<int, 64> ConcatMask;
@@ -58153,10 +58156,14 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
}
}
if (ConcatMask.size() == (NumOps * NumSrcElts)) {
- SDValue Src0 = ConcatSubOperand(VT, Ops, 0);
- SDValue Src1 = ConcatSubOperand(VT, Ops, 2);
- return lowerShuffleWithPERMV(DL, VT, ConcatMask, Src0, Src1,
- Subtarget, DAG);
+ SDValue Concat0 = CombineSubOperand(VT, Ops, 0);
+ SDValue Concat1 = CombineSubOperand(VT, Ops, 2);
+ if (Concat0 || Concat1)
+ return lowerShuffleWithPERMV(
+ DL, VT, ConcatMask,
+ Concat0 ? Concat0 : ConcatSubOperand(VT, Ops, 0),
+ Concat1 ? Concat1 : ConcatSubOperand(VT, Ops, 2), Subtarget,
+ DAG);
}
}
break;
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll b/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
index 9f69a3cf44189..81fe19c4d8b56 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
@@ -1049,24 +1049,24 @@ define void @load_i8_stride2_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nou
; AVX512-FCP-NEXT: vmovdqa 64(%rdi), %ymm3
; AVX512-FCP-NEXT: vmovdqa 96(%rdi), %ymm4
; AVX512-FCP-NEXT: vpshufb %ymm0, %ymm4, %ymm5
+; AVX512-FCP-NEXT: vpbroadcastq {{.*#+}} ymm6 = [0,2,4,6,8,10,12,14,0,2,4,6,8,10,12,14,0,2,4,6,8,10,12,14,0,2,4,6,8,10,12,14]
+; AVX512-FCP-NEXT: vpshufb %ymm6, %ymm3, %ymm7
+; AVX512-FCP-NEXT: vpmovsxbq {{.*#+}} ymm8 = [0,2,5,7]
+; AVX512-FCP-NEXT: vpermt2q %ymm5, %ymm8, %ymm7
; AVX512-FCP-NEXT: vpshufb %ymm0, %ymm2, %ymm0
-; AVX512-FCP-NEXT: vinserti64x4 $1, %ymm5, %zmm0, %zmm0
-; AVX512-FCP-NEXT: vpbroadcastq {{.*#+}} ymm5 = [0,2,4,6,8,10,12,14,0,2,4,6,8,10,12,14,0,2,4,6,8,10,12,14,0,2,4,6,8,10,12,14]
-; AVX512-FCP-NEXT: vpshufb %ymm5, %ymm3, %ymm6
-; AVX512-FCP-NEXT: vpshufb %ymm5, %ymm1, %ymm5
-; AVX512-FCP-NEXT: vinserti64x4 $1, %ymm6, %zmm5, %zmm5
-; AVX512-FCP-NEXT: vpmovsxbq {{.*#+}} zmm6 = [0,2,9,11,4,6,13,15]
-; AVX512-FCP-NEXT: vpermt2q %zmm0, %zmm6, %zmm5
-; AVX512-FCP-NEXT: vpbroadcastq {{.*#+}} ymm0 = [1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15]
-; AVX512-FCP-NEXT: vpshufb %ymm0, %ymm4, %ymm4
-; AVX512-FCP-NEXT: vpshufb %ymm0, %ymm2, %ymm0
-; AVX512-FCP-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm0
-; AVX512-FCP-NEXT: vpbroadcastq {{.*#+}} ymm2 = [1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15]
-; AVX512-FCP-NEXT: vpshufb %ymm2, %ymm3, %ymm3
-; AVX512-FCP-NEXT: vpshufb %ymm2, %ymm1, %ymm1
+; AVX512-FCP-NEXT: vpshufb %ymm6, %ymm1, %ymm5
+; AVX512-FCP-NEXT: vpermt2q %ymm0, %ymm8, %ymm5
+; AVX512-FCP-NEXT: vinserti64x4 $1, %ymm7, %zmm5, %zmm0
+; AVX512-FCP-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15]
+; AVX512-FCP-NEXT: vpshufb %ymm5, %ymm4, %ymm4
+; AVX512-FCP-NEXT: vpbroadcastq {{.*#+}} ymm6 = [1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15]
+; AVX512-FCP-NEXT: vpshufb %ymm6, %ymm3, %ymm3
+; AVX512-FCP-NEXT: vpermt2q %ymm4, %ymm8, %ymm3
+; AVX512-FCP-NEXT: vpshufb %ymm5, %ymm2, %ymm2
+; AVX512-FCP-NEXT: vpshufb %ymm6, %ymm1, %ymm1
+; AVX512-FCP-NEXT: vpermt2q %ymm2, %ymm8, %ymm1
; AVX512-FCP-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1
-; AVX512-FCP-NEXT: vpermt2q %zmm0, %zmm6, %zmm1
-; AVX512-FCP-NEXT: vmovdqa64 %zmm5, (%rsi)
+; AVX512-FCP-NEXT: vmovdqa64 %zmm0, (%rsi)
; AVX512-FCP-NEXT: vmovdqa64 %zmm1, (%rdx)
; AVX512-FCP-NEXT: vzeroupper
; AVX512-FCP-NEXT: retq
@@ -1110,24 +1110,24 @@ define void @load_i8_stride2_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) nou
; AVX512DQ-FCP-NEXT: vmovdqa 64(%rdi), %ymm3
; AVX512DQ-FCP-NEXT: vmovdqa 96(%rdi), %ymm4
; AVX512DQ-FCP-NEXT: vpshufb %ymm0, %ymm4, %ymm5
+; AVX512DQ-FCP-NEXT: vpbroadcastq {{.*#+}} ymm6 = [0,2,4,6,8,10,12,14,0,2,4,6,8,10,12,14,0,2,4,6,8,10,12,14,0,2,4,6,8,10,12,14]
+; AVX512DQ-FCP-NEXT: vpshufb %ymm6, %ymm3, %ymm7
+; AVX512DQ-FCP-NEXT: vpmovsxbq {{.*#+}} ymm8 = [0,2,5,7]
+; AVX512DQ-FCP-NEXT: vpermt2q %ymm5, %ymm8, %ymm7
; AVX512DQ-FCP-NEXT: vpshufb %ymm0, %ymm2, %ymm0
-; AVX512DQ-FCP-NEXT: vinserti64x4 $1, %ymm5, %zmm0, %zmm0
-; AVX512DQ-FCP-NEXT: vpbroadcastq {{.*#+}} ymm5 = [0,2,4,6,8,10,12,14,0,2,4,6,8,10,12,14,0,2,4,6,8,10,12,14,0,2,4,6,8,10,12,14]
-; AVX512DQ-FCP-NEXT: vpshufb %ymm5, %ymm3, %ymm6
-; AVX512DQ-FCP-NEXT: vpshufb %ymm5, %ymm1, %ymm5
-; AVX512DQ-FCP-NEXT: vinserti64x4 $1, %ymm6, %zmm5, %zmm5
-; AVX512DQ-FCP-NEXT: vpmovsxbq {{.*#+}} zmm6 = [0,2,9,11,4,6,13,15]
-; AVX512DQ-FCP-NEXT: vpermt2q %zmm0, %zmm6, %zmm5
-; AVX512DQ-FCP-NEXT: vpbroadcastq {{.*#+}} ymm0 = [1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15]
-; AVX512DQ-FCP-NEXT: vpshufb %ymm0, %ymm4, %ymm4
-; AVX512DQ-FCP-NEXT: vpshufb %ymm0, %ymm2, %ymm0
-; AVX512DQ-FCP-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm0
-; AVX512DQ-FCP-NEXT: vpbroadcastq {{.*#+}} ymm2 = [1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15]
-; AVX512DQ-FCP-NEXT: vpshufb %ymm2, %ymm3, %ymm3
-; AVX512DQ-FCP-NEXT: vpshufb %ymm2, %ymm1, %ymm1
+; AVX512DQ-FCP-NEXT: vpshufb %ymm6, %ymm1, %ymm5
+; AVX512DQ-FCP-NEXT: vpermt2q %ymm0, %ymm8, %ymm5
+; AVX512DQ-FCP-NEXT: vinserti64x4 $1, %ymm7, %zmm5, %zmm0
+; AVX512DQ-FCP-NEXT: vpbroadcastq {{.*#+}} ymm5 = [1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15]
+; AVX512DQ-FCP-NEXT: vpshufb %ymm5, %ymm4, %ymm4
+; AVX512DQ-FCP-NEXT: vpbroadcastq {{.*#+}} ymm6 = [1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15,1,3,5,7,9,11,13,15]
+; AVX512DQ-FCP-NEXT: vpshufb %ymm6, %ymm3, %ymm3
+; AVX512DQ-FCP-NEXT: vpermt2q %ymm4, %ymm8, %ymm3
+; AVX512DQ-FCP-NEXT: vpshufb %ymm5, %ymm2, %ymm2
+; AVX512DQ-FCP-NEXT: vpshufb %ymm6, %ymm1, %ymm1
+; AVX512DQ-FCP-NEXT: vpermt2q %ymm2, %ymm8, %ymm1
; AVX512DQ-FCP-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1
-; AVX512DQ-FCP-NEXT: vpermt2q %zmm0, %zmm6, %zmm1
-; AVX512DQ-FCP-NEXT: vmovdqa64 %zmm5, (%rsi)
+; AVX512DQ-FCP-NEXT: vmovdqa64 %zmm0, (%rsi)
; AVX512DQ-FCP-NEXT: vmovdqa64 %zmm1, (%rdx)
; AVX512DQ-FCP-NEXT: vzeroupper
; AVX512DQ-FCP-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
index cec376e729205..2f6452467a420 100644
--- a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
+++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
@@ -921,26 +921,26 @@ define void @store_i16_stride4_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX512-NEXT: vmovdqa (%rdx), %xmm2
; AVX512-NEXT: vmovdqa 16(%rdx), %xmm3
; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
+; AVX512-NEXT: vmovdqa (%rsi), %xmm5
+; AVX512-NEXT: vmovdqa 16(%rsi), %xmm6
+; AVX512-NEXT: vmovdqa (%rdi), %xmm7
+; AVX512-NEXT: vmovdqa 16(%rdi), %xmm8
+; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm9 = xmm8[4],xmm6[4],xmm8[5],xmm6[5],xmm8[6],xmm6[6],xmm8[7],xmm6[7]
+; AVX512-NEXT: vpmovsxbd {{.*#+}} ymm10 = [0,8,1,9,2,10,3,11]
+; AVX512-NEXT: vpermt2d %ymm4, %ymm10, %ymm9
; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3]
-; AVX512-NEXT: vinserti32x4 $2, %xmm4, %zmm1, %zmm1
-; AVX512-NEXT: vmovdqa (%rsi), %xmm3
-; AVX512-NEXT: vmovdqa 16(%rsi), %xmm4
-; AVX512-NEXT: vmovdqa (%rdi), %xmm5
-; AVX512-NEXT: vmovdqa 16(%rdi), %xmm6
-; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm7 = xmm6[4],xmm4[4],xmm6[5],xmm4[5],xmm6[6],xmm4[6],xmm6[7],xmm4[7]
-; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm6[0],xmm4[0],xmm6[1],xmm4[1],xmm6[2],xmm4[2],xmm6[3],xmm4[3]
-; AVX512-NEXT: vinserti32x4 $2, %xmm7, %zmm4, %zmm4
-; AVX512-NEXT: vpmovsxbd {{.*#+}} zmm6 = [0,16,1,17,2,18,3,19,8,24,9,25,10,26,11,27]
-; AVX512-NEXT: vpermt2d %zmm1, %zmm6, %zmm4
-; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm8[0],xmm6[0],xmm8[1],xmm6[1],xmm8[2],xmm6[2],xmm8[3],xmm6[3]
+; AVX512-NEXT: vpermt2d %ymm1, %ymm10, %ymm3
+; AVX512-NEXT: vinserti64x4 $1, %ymm9, %zmm3, %zmm1
+; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm7[4],xmm5[4],xmm7[5],xmm5[5],xmm7[6],xmm5[6],xmm7[7],xmm5[7]
+; AVX512-NEXT: vpermt2d %ymm3, %ymm10, %ymm4
; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
-; AVX512-NEXT: vinserti32x4 $2, %xmm1, %zmm0, %zmm0
-; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm5[4],xmm3[4],xmm5[5],xmm3[5],xmm5[6],xmm3[6],xmm5[7],xmm3[7]
-; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm5[0],xmm3[0],xmm5[1],xmm3[1],xmm5[2],xmm3[2],xmm5[3],xmm3[3]
-; AVX512-NEXT: vinserti32x4 $2, %xmm1, %zmm2, %zmm1
-; AVX512-NEXT: vpermt2d %zmm0, %zmm6, %zmm1
-; AVX512-NEXT: vmovdqa64 %zmm1, (%r8)
-; AVX512-NEXT: vmovdqa64 %zmm4, 64(%r8)
+; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3]
+; AVX512-NEXT: vpermt2d %ymm0, %ymm10, %ymm2
+; AVX512-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm0
+; AVX512-NEXT: vmovdqa64 %zmm0, (%r8)
+; AVX512-NEXT: vmovdqa64 %zmm1, 64(%r8)
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
;
@@ -951,26 +951,26 @@ define void @store_i16_stride4_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX512-FCP-NEXT: vmovdqa (%rdx), %xmm2
; AVX512-FCP-NEXT: vmovdqa 16(%rdx), %xmm3
; AVX512-FCP-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
+; AVX512-FCP-NEXT: vmovdqa (%rsi), %xmm5
+; AVX512-FCP-NEXT: vmovdqa 16(%rsi), %xmm6
+; AVX512-FCP-NEXT: vmovdqa (%rdi), %xmm7
+; AVX512-FCP-NEXT: vmovdqa 16(%rdi), %xmm8
+; AVX512-FCP-NEXT: vpunpckhwd {{.*#+}} xmm9 = xmm8[4],xmm6[4],xmm8[5],xmm6[5],xmm8[6],xmm6[6],xmm8[7],xmm6[7]
+; AVX512-FCP-NEXT: vpmovsxbd {{.*#+}} ymm10 = [0,8,1,9,2,10,3,11]
+; AVX512-FCP-NEXT: vpermt2d %ymm4, %ymm10, %ymm9
; AVX512-FCP-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3]
-; AVX512-FCP-NEXT: vinserti32x4 $2, %xmm4, %zmm1, %zmm1
-; AVX512-FCP-NEXT: vmovdqa (%rsi), %xmm3
-; AVX512-FCP-NEXT: vmovdqa 16(%rsi), %xmm4
-; AVX512-FCP-NEXT: vmovdqa (%rdi), %xmm5
-; AVX512-FCP-NEXT: vmovdqa 16(%rdi), %xmm6
-; AVX512-FCP-NEXT: vpunpckhwd {{.*#+}} xmm7 = xmm6[4],xmm4[4],xmm6[5],xmm4[5],xmm6[6],xmm4[6],xmm6[7],xmm4[7]
-; AVX512-FCP-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm6[0],xmm4[0],xmm6[1],xmm4[1],xmm6[2],xmm4[2],xmm6[3],xmm4[3]
-; AVX512-FCP-NEXT: vinserti32x4 $2, %xmm7, %zmm4, %zmm4
-; AVX512-FCP-NEXT: vpmovsxbd {{.*#+}} zmm6 = [0,16,1,17,2,18,3,19,8,24,9,25,10,26,11,27]
-; AVX512-FCP-NEXT: vpermt2d %zmm1, %zmm6, %zmm4
-; AVX512-FCP-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; AVX512-FCP-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm8[0],xmm6[0],xmm8[1],xmm6[1],xmm8[2],xmm6[2],xmm8[3],xmm6[3]
+; AVX512-FCP-NEXT: vpermt2d %ymm1, %ymm10, %ymm3
+; AVX512-FCP-NEXT: vinserti64x4 $1, %ymm9, %zmm3, %zmm1
+; AVX512-FCP-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; AVX512-FCP-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm7[4],xmm5[4],xmm7[5],xmm5[5],xmm7[6],xmm5[6],xmm7[7],xmm5[7]
+; AVX512-FCP-NEXT: vpermt2d %ymm3, %ymm10, %ymm4
; AVX512-FCP-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
-; AVX512-FCP-NEXT: vinserti32x4 $2, %xmm1, %zmm0, %zmm0
-; AVX512-FCP-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm5[4],xmm3[4],xmm5[5],xmm3[5],xmm5[6],xmm3[6],xmm5[7],xmm3[7]
-; AVX512-FCP-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm5[0],xmm3[0],xmm5[1],xmm3[1],xmm5[2],xmm3[2],xmm5[3],xmm3[3]
-; AVX512-FCP-NEXT: vinserti32x4 $2, %xmm1, %zmm2, %zmm1
-; AVX512-FCP-NEXT: vpermt2d %zmm0, %zmm6, %zmm1
-; AVX512-FCP-NEXT: vmovdqa64 %zmm1, (%r8)
-; AVX512-FCP-NEXT: vmovdqa64 %zmm4, 64(%r8)
+; AVX512-FCP-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3]
+; AVX512-FCP-NEXT: vpermt2d %ymm0, %ymm10, %ymm2
+; AVX512-FCP-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm0
+; AVX512-FCP-NEXT: vmovdqa64 %zmm0, (%r8)
+; AVX512-FCP-NEXT: vmovdqa64 %zmm1, 64(%r8)
; AVX512-FCP-NEXT: vzeroupper
; AVX512-FCP-NEXT: retq
;
@@ -981,26 +981,26 @@ define void @store_i16_stride4_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX512DQ-NEXT: vmovdqa (%rdx), %xmm2
; AVX512DQ-NEXT: vmovdqa 16(%rdx), %xmm3
; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
+; AVX512DQ-NEXT: vmovdqa (%rsi), %xmm5
+; AVX512DQ-NEXT: vmovdqa 16(%rsi), %xmm6
+; AVX512DQ-NEXT: vmovdqa (%rdi), %xmm7
+; AVX512DQ-NEXT: vmovdqa 16(%rdi), %xmm8
+; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm9 = xmm8[4],xmm6[4],xmm8[5],xmm6[5],xmm8[6],xmm6[6],xmm8[7],xmm6[7]
+; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} ymm10 = [0,8,1,9,2,10,3,11]
+; AVX512DQ-NEXT: vpermt2d %ymm4, %ymm10, %ymm9
; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3]
-; AVX512DQ-NEXT: vinserti32x4 $2, %xmm4, %zmm1, %zmm1
-; AVX512DQ-NEXT: vmovdqa (%rsi), %xmm3
-; AVX512DQ-NEXT: vmovdqa 16(%rsi), %xmm4
-; AVX512DQ-NEXT: vmovdqa (%rdi), %xmm5
-; AVX512DQ-NEXT: vmovdqa 16(%rdi), %xmm6
-; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm7 = xmm6[4],xmm4[4],xmm6[5],xmm4[5],xmm6[6],xmm4[6],xmm6[7],xmm4[7]
-; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm6[0],xmm4[0],xmm6[1],xmm4[1],xmm6[2],xmm4[2],xmm6[3],xmm4[3]
-; AVX512DQ-NEXT: vinserti32x4 $2, %xmm7, %zmm4, %zmm4
-; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} zmm6 = [0,16,1,17,2,18,3,19,8,24,9,25,10,26,11,27]
-; AVX512DQ-NEXT: vpermt2d %zmm1, %zmm6, %zmm4
-; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm8[0],xmm6[0],xmm8[1],xmm6[1],xmm8[2],xmm6[2],xmm8[3],xmm6[3]
+; AVX512DQ-NEXT: vpermt2d %ymm1, %ymm10, %ymm3
+; AVX512DQ-NEXT: vinserti64x4 $1, %ymm9, %zmm3, %zmm1
+; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm7[4],xmm5[4],xmm7[5],xmm5[5],xmm7[6],xmm5[6],xmm7[7],xmm5[7]
+; AVX512DQ-NEXT: vpermt2d %ymm3, %ymm10, %ymm4
; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
-; AVX512DQ-NEXT: vinserti32x4 $2, %xmm1, %zmm0, %zmm0
-; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm5[4],xmm3[4],xmm5[5],xmm3[5],xmm5[6],xmm3[6],xmm5[7],xmm3[7]
-; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm5[0],xmm3[0],xmm5[1],xmm3[1],xmm5[2],xmm3[2],xmm5[3],xmm3[3]
-; AVX512DQ-NEXT: vinserti32x4 $2, %xmm1, %zmm2, %zmm1
-; AVX512DQ-NEXT: vpermt2d %zmm0, %zmm6, %zmm1
-; AVX512DQ-NEXT: vmovdqa64 %zmm1, (%r8)
-; AVX512DQ-NEXT: vmovdqa64 %zmm4, 64(%r8)
+; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3]
+; AVX512DQ-NEXT: vpermt2d %ymm0, %ymm10, %ymm2
+; AVX512DQ-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm0
+; AVX512DQ-NEXT: vmovdqa64 %zmm0, (%r8)
+; AVX512DQ-NEXT: vmovdqa64 %zmm1, 64(%r8)
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
;
@@ -1011,26 +1011,26 @@ define void @store_i16_stride4_vf16(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve
; AVX512DQ-FCP-NEXT: vmovdqa (%rdx), %xmm2
; AVX512DQ-FCP-NEXT: vmovdqa 16(%rdx), %xmm3
; AVX512DQ-FCP-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
+; AVX512DQ-FCP-NEXT: vmovdqa (%rsi), %xmm5
+; AVX512DQ-FCP-NEXT: vmovdqa 16(%rsi), %xmm6
+; AVX512DQ-FCP-NEXT: vmovdqa (%rdi), %xmm7
+; AVX512DQ-FCP-NEXT: vmovdqa 16(%rdi), %xmm8
+; AVX512DQ-FCP-NEXT: vpunpckhwd {{.*#+}} xmm9 = xmm8[4],xmm6[4],xmm8[5],xmm6[5],xmm8[6],xmm6[6],xmm8[7],xmm6[7]
+; AVX512DQ-FCP-NEXT: vpmovsxbd {{.*#+}} ymm10 = [0,8,1,9,2,10,3,11]
+; AVX512DQ-FCP-NEXT: vpermt2d %ymm4, %ymm10, %ymm9
; AVX512DQ-FCP-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3]
-; AVX512DQ-FCP-NEXT: vinserti32x4 $2, %xmm4, %zmm1, %zmm1
-; AVX512DQ-FCP-NEXT: vmovdqa (%rsi), %xmm3
-; AVX512DQ-FCP-NEXT: vmovdqa 16(%rsi), %xmm4
-; AVX512DQ-FCP-NEXT: vmovdqa (%rdi), %xmm5
-; AVX512DQ-FCP-NEXT: vmovdqa 16(%rdi), %xmm6
-; AVX512DQ-FCP-NEXT: vpunpckhwd {{.*#+}} xmm7 = xmm6[4],xmm4[4],xmm6[5],xmm4[5],xmm6[6],xmm4[6],xmm6[7],xmm4[7]
-; AVX512DQ-FCP-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm6[0],xmm4[0],xmm6[1],xmm4[1],xmm6[2],xmm4[2],xmm6[3],xmm4[3]
-; AVX512DQ-FCP-NEXT: vinserti32x4 $2, %xmm7, %zmm4, %zmm4
-; AVX512DQ-FCP-NEXT: vpmovsxbd {{.*#+}} zmm6 = [0,16,1,17,2,18,3,19,8,24,9,25,10,26,11,27]
-; AVX512DQ-FCP-NEXT: vpermt2d %zmm1, %zmm6, %zmm4
-; AVX512DQ-FCP-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; AVX512DQ-FCP-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm8[0],xmm6[0],xmm8[1],xmm6[1],xmm8[2],xmm6[2],xmm8[3],xmm6[3]
+; AVX512DQ-FCP-NEXT: vpermt2d %ymm1, %ymm10, %ymm3
+; AVX512DQ-FCP-NEXT: vinserti64x4 $1, %ymm9, %zmm3, %zmm1
+; AVX512DQ-FCP-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; AVX512DQ-FCP-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm7[4],xmm5[4],xmm7[5],xmm5[5],xmm7[6],xmm5[6],xmm7[7],xmm5[7]
+; AVX512DQ-FCP-NEXT: vpermt2d %ymm3, %ymm10, %ymm4
; AVX512DQ-FCP-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
-; AVX512DQ-FCP-NEXT: vinserti32x4 $2, %xmm1, %zmm0, %zmm0
-; AVX512DQ-FCP-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm5[4],xmm3[4],xmm5[5],xmm3[5],xmm5[6],xmm3[6],xmm5[7],xmm3[7]
-; AVX512DQ-FCP-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm5[0],xmm3[0],xmm5[1],xmm3[1],xmm5[2],xmm3[2],xmm5[3],xmm3[3]
-; AVX512DQ-FCP-NEXT: vinserti32x4 $2, %xmm1, %zmm2, %zmm1
-; AVX512DQ-FCP-NEXT: vpermt2d %zmm0, %zmm6, %zmm1
-; AVX512DQ-FCP-NEXT: vmovdqa64 %zmm1, (%r8)
-; AVX512DQ-FCP-NEXT: vmovdqa64 %zmm4, 64(%r8)
+; AVX512DQ-FCP-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3]
+; AVX512DQ-FCP-NEXT: vpermt2d %ymm0, %ymm10, %ymm2
+; AVX512DQ-FCP-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm0
+; AVX512DQ-FCP-NEXT: vmovdqa64 %zmm0, (%r8)
+; AVX512DQ-FCP-NEXT: vmovdqa64 %zmm1, 64(%r8)
; AVX512DQ-FCP-NEXT: vzeroupper
; AVX512DQ-FCP-NEXT: retq
;
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