[llvm] [X86] combineConcatVectorOps - add support for AVX1 and/or/xor/andnp concatenation (PR #130645)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 10 10:48:38 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: Simon Pilgrim (RKSimon)
<details>
<summary>Changes</summary>
Limit AVX1-only targets to cases where at least one operand is beneficial to concatenate, but avoid unnecessary 256-bit NOT patterns unless it allows further folds.
There are still a large number of regressions when limiting AVX2+ targets to beneficial concatenation - so added a TODO for now.
---
Patch is 507.55 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/130645.diff
21 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+14-4)
- (modified) llvm/test/CodeGen/X86/avx-shift.ll (+8-12)
- (modified) llvm/test/CodeGen/X86/gfni-shifts.ll (+36-40)
- (modified) llvm/test/CodeGen/X86/known-bits-vector.ll (+4-8)
- (modified) llvm/test/CodeGen/X86/pmul.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/vector-fshl-256.ll (+8-12)
- (modified) llvm/test/CodeGen/X86/vector-fshl-rot-256.ll (+10-12)
- (modified) llvm/test/CodeGen/X86/vector-fshr-256.ll (+24-30)
- (modified) llvm/test/CodeGen/X86/vector-fshr-rot-256.ll (+10-12)
- (modified) llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll (+24-26)
- (modified) llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll (+12-12)
- (modified) llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll (+180-180)
- (modified) llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll (+84-84)
- (modified) llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll (+658-656)
- (modified) llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll (+464-470)
- (modified) llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll (+56-56)
- (modified) llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll (+80-100)
- (modified) llvm/test/CodeGen/X86/vector-rotate-256.ll (+20-24)
- (modified) llvm/test/CodeGen/X86/vector-shift-lshr-256.ll (+12-22)
- (modified) llvm/test/CodeGen/X86/vector-shift-shl-256.ll (+36-48)
- (modified) llvm/test/CodeGen/X86/vector-shuffle-v192.ll (+2-2)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index aec071f038dc6..b27d9da922b22 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -58304,11 +58304,21 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
case ISD::OR:
case ISD::XOR:
case X86ISD::ANDNP:
- if (!IsSplat && ((VT.is256BitVector() && Subtarget.hasInt256()) ||
+ // TODO: AVX2+ targets should only use CombineSubOperand like AVX1.
+ if (!IsSplat && (VT.is256BitVector() ||
(VT.is512BitVector() && Subtarget.useAVX512Regs()))) {
- return DAG.getNode(Op0.getOpcode(), DL, VT,
- ConcatSubOperand(VT, Ops, 0),
- ConcatSubOperand(VT, Ops, 1));
+ // Don't concatenate root AVX1 NOT patterns.
+ if (Op0.getOpcode() == ISD::XOR && Depth == 0 &&
+ !Subtarget.hasInt256() && llvm::all_of(Ops, [](SDValue X) {
+ return ISD::isBuildVectorAllOnes(X.getOperand(1).getNode());
+ }))
+ break;
+ SDValue Concat0 = CombineSubOperand(VT, Ops, 0);
+ SDValue Concat1 = CombineSubOperand(VT, Ops, 1);
+ if (Concat0 || Concat1 || Subtarget.hasInt256())
+ return DAG.getNode(Op0.getOpcode(), DL, VT,
+ Concat0 ? Concat0 : ConcatSubOperand(VT, Ops, 0),
+ Concat1 ? Concat1 : ConcatSubOperand(VT, Ops, 1));
}
break;
case X86ISD::PCMPEQ:
diff --git a/llvm/test/CodeGen/X86/avx-shift.ll b/llvm/test/CodeGen/X86/avx-shift.ll
index 1da78ebd75b14..c9c09d7d10346 100644
--- a/llvm/test/CodeGen/X86/avx-shift.ll
+++ b/llvm/test/CodeGen/X86/avx-shift.ll
@@ -136,13 +136,11 @@ define <32 x i8> @vshift10(<32 x i8> %a) {
define <32 x i8> @vshift11(<32 x i8> %a) {
; CHECK-LABEL: vshift11:
; CHECK: # %bb.0:
-; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
-; CHECK-NEXT: vpsrlw $2, %xmm1, %xmm1
-; CHECK-NEXT: vbroadcastss {{.*#+}} xmm2 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
-; CHECK-NEXT: vpand %xmm2, %xmm1, %xmm1
+; CHECK-NEXT: vpsrlw $2, %xmm0, %xmm1
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
; CHECK-NEXT: vpsrlw $2, %xmm0, %xmm0
-; CHECK-NEXT: vpand %xmm2, %xmm0, %xmm0
-; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%s = lshr <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
ret <32 x i8> %s
@@ -151,13 +149,11 @@ define <32 x i8> @vshift11(<32 x i8> %a) {
define <32 x i8> @vshift12(<32 x i8> %a) {
; CHECK-LABEL: vshift12:
; CHECK: # %bb.0:
-; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
-; CHECK-NEXT: vpsllw $2, %xmm1, %xmm1
-; CHECK-NEXT: vbroadcastss {{.*#+}} xmm2 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
-; CHECK-NEXT: vpand %xmm2, %xmm1, %xmm1
+; CHECK-NEXT: vpsllw $2, %xmm0, %xmm1
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
; CHECK-NEXT: vpsllw $2, %xmm0, %xmm0
-; CHECK-NEXT: vpand %xmm2, %xmm0, %xmm0
-; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; CHECK-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: retq
%s = shl <32 x i8> %a, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
ret <32 x i8> %s
diff --git a/llvm/test/CodeGen/X86/gfni-shifts.ll b/llvm/test/CodeGen/X86/gfni-shifts.ll
index 38f6cabd21fba..5cd1a2c76762e 100644
--- a/llvm/test/CodeGen/X86/gfni-shifts.ll
+++ b/llvm/test/CodeGen/X86/gfni-shifts.ll
@@ -1232,21 +1232,19 @@ define <32 x i8> @constant_shl_v32i8(<32 x i8> %a) nounwind {
;
; GFNIAVX1-LABEL: constant_shl_v32i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; GFNIAVX1-NEXT: vpmovzxbw {{.*#+}} xmm2 = [1,4,16,64,128,32,8,2]
-; GFNIAVX1-NEXT: vpmaddubsw %xmm2, %xmm1, %xmm3
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [255,255,255,255,255,255,255,255]
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]
-; GFNIAVX1-NEXT: vpmaddubsw %xmm5, %xmm1, %xmm1
+; GFNIAVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]
+; GFNIAVX1-NEXT: vpmaddubsw %xmm1, %xmm0, %xmm2
+; GFNIAVX1-NEXT: vpsllw $8, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
+; GFNIAVX1-NEXT: vpmaddubsw %xmm1, %xmm3, %xmm1
; GFNIAVX1-NEXT: vpsllw $8, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpor %xmm1, %xmm3, %xmm1
-; GFNIAVX1-NEXT: vpmaddubsw %xmm2, %xmm0, %xmm2
-; GFNIAVX1-NEXT: vpand %xmm4, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpmaddubsw %xmm5, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsllw $8, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpor %xmm0, %xmm2, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
+; GFNIAVX1-NEXT: vpmovzxbw {{.*#+}} xmm2 = [1,4,16,64,128,32,8,2]
+; GFNIAVX1-NEXT: vpmaddubsw %xmm2, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vpmaddubsw %xmm2, %xmm0, %xmm0
+; GFNIAVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; GFNIAVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: constant_shl_v32i8:
@@ -2575,33 +2573,31 @@ define <64 x i8> @constant_shl_v64i8(<64 x i8> %a) nounwind {
;
; GFNIAVX1-LABEL: constant_shl_v64i8:
; GFNIAVX1: # %bb.0:
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; GFNIAVX1-NEXT: vpmovzxbw {{.*#+}} xmm3 = [1,4,16,64,128,32,8,2]
-; GFNIAVX1-NEXT: vpmaddubsw %xmm3, %xmm2, %xmm4
-; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [255,255,255,255,255,255,255,255]
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
-; GFNIAVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]
-; GFNIAVX1-NEXT: vpmaddubsw %xmm6, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpsllw $8, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpor %xmm2, %xmm4, %xmm2
-; GFNIAVX1-NEXT: vpmaddubsw %xmm3, %xmm0, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
-; GFNIAVX1-NEXT: vpmaddubsw %xmm6, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpsllw $8, %xmm0, %xmm0
-; GFNIAVX1-NEXT: vpor %xmm0, %xmm4, %xmm0
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
-; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; GFNIAVX1-NEXT: vpmaddubsw %xmm3, %xmm2, %xmm4
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
-; GFNIAVX1-NEXT: vpmaddubsw %xmm6, %xmm2, %xmm2
+; GFNIAVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]
+; GFNIAVX1-NEXT: vpmaddubsw %xmm2, %xmm0, %xmm3
+; GFNIAVX1-NEXT: vpsllw $8, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
+; GFNIAVX1-NEXT: vpmaddubsw %xmm2, %xmm4, %xmm5
+; GFNIAVX1-NEXT: vpsllw $8, %xmm5, %xmm5
+; GFNIAVX1-NEXT: vinsertf128 $1, %xmm5, %ymm3, %ymm3
+; GFNIAVX1-NEXT: vpmovzxbw {{.*#+}} xmm5 = [1,4,16,64,128,32,8,2]
+; GFNIAVX1-NEXT: vpmaddubsw %xmm5, %xmm4, %xmm4
+; GFNIAVX1-NEXT: vpmaddubsw %xmm5, %xmm0, %xmm0
+; GFNIAVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} ymm4 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
+; GFNIAVX1-NEXT: vandps %ymm4, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vorps %ymm3, %ymm0, %ymm0
+; GFNIAVX1-NEXT: vpmaddubsw %xmm2, %xmm1, %xmm3
+; GFNIAVX1-NEXT: vpsllw $8, %xmm3, %xmm3
+; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm6
+; GFNIAVX1-NEXT: vpmaddubsw %xmm2, %xmm6, %xmm2
; GFNIAVX1-NEXT: vpsllw $8, %xmm2, %xmm2
-; GFNIAVX1-NEXT: vpor %xmm2, %xmm4, %xmm2
-; GFNIAVX1-NEXT: vpmaddubsw %xmm3, %xmm1, %xmm3
-; GFNIAVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
-; GFNIAVX1-NEXT: vpmaddubsw %xmm6, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpsllw $8, %xmm1, %xmm1
-; GFNIAVX1-NEXT: vpor %xmm1, %xmm3, %xmm1
-; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
+; GFNIAVX1-NEXT: vpmaddubsw %xmm5, %xmm6, %xmm3
+; GFNIAVX1-NEXT: vpmaddubsw %xmm5, %xmm1, %xmm1
+; GFNIAVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
+; GFNIAVX1-NEXT: vandps %ymm4, %ymm1, %ymm1
+; GFNIAVX1-NEXT: vorps %ymm2, %ymm1, %ymm1
; GFNIAVX1-NEXT: retq
;
; GFNIAVX2-LABEL: constant_shl_v64i8:
diff --git a/llvm/test/CodeGen/X86/known-bits-vector.ll b/llvm/test/CodeGen/X86/known-bits-vector.ll
index 2eef32eb61414..dbf3d6635fb92 100644
--- a/llvm/test/CodeGen/X86/known-bits-vector.ll
+++ b/llvm/test/CodeGen/X86/known-bits-vector.ll
@@ -384,23 +384,19 @@ declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
define <8 x float> @knownbits_mask_concat_uitofp(<4 x i32> %a0, <4 x i32> %a1) nounwind {
; X86-LABEL: knownbits_mask_concat_uitofp:
; X86: # %bb.0:
-; X86-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,3,1,3]
-; X86-NEXT: vbroadcastss {{.*#+}} xmm2 = [131071,131071,131071,131071]
-; X86-NEXT: vandps %xmm2, %xmm1, %xmm1
; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,0,2]
-; X86-NEXT: vandps %xmm2, %xmm0, %xmm0
+; X86-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,3,1,3]
; X86-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: vcvtdq2ps %ymm0, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: knownbits_mask_concat_uitofp:
; X64: # %bb.0:
-; X64-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,3,1,3]
-; X64-NEXT: vbroadcastss {{.*#+}} xmm2 = [131071,131071,131071,131071]
-; X64-NEXT: vandps %xmm2, %xmm1, %xmm1
; X64-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,0,2]
-; X64-NEXT: vandps %xmm2, %xmm0, %xmm0
+; X64-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,3,1,3]
; X64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vcvtdq2ps %ymm0, %ymm0
; X64-NEXT: retq
%1 = and <4 x i32> %a0, <i32 131071, i32 -1, i32 131071, i32 -1>
diff --git a/llvm/test/CodeGen/X86/pmul.ll b/llvm/test/CodeGen/X86/pmul.ll
index fe8a4fa163129..c7cc2acaf2627 100644
--- a/llvm/test/CodeGen/X86/pmul.ll
+++ b/llvm/test/CodeGen/X86/pmul.ll
@@ -959,7 +959,7 @@ define <64 x i8> @mul_v64i8(<64 x i8> %i, <64 x i8> %j) nounwind {
;
; AVX512F-LABEL: mul_v64i8:
; AVX512F: # %bb.0: # %entry
-; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
+; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm3
; AVX512F-NEXT: vpand %ymm2, %ymm3, %ymm4
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm5
diff --git a/llvm/test/CodeGen/X86/vector-fshl-256.ll b/llvm/test/CodeGen/X86/vector-fshl-256.ll
index 6fb74643e4bb7..fdd0d68b89003 100644
--- a/llvm/test/CodeGen/X86/vector-fshl-256.ll
+++ b/llvm/test/CodeGen/X86/vector-fshl-256.ll
@@ -2270,20 +2270,16 @@ define <16 x i16> @splatconstant_funnnel_v16i16(<16 x i16> %x, <16 x i16> %y) no
define <32 x i8> @splatconstant_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
; AVX1-LABEL: splatconstant_funnnel_v32i8:
; AVX1: # %bb.0:
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm2
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT: vpsllw $4, %xmm2, %xmm2
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vpsllw $4, %xmm0, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpsllw $4, %xmm0, %xmm0
-; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-fshl-rot-256.ll b/llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
index 9806d63257180..f0f3d6028c27a 100644
--- a/llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
+++ b/llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
@@ -1623,19 +1623,17 @@ define <16 x i16> @splatconstant_funnnel_v16i16(<16 x i16> %x) nounwind {
define <32 x i8> @splatconstant_funnnel_v32i8(<32 x i8> %x) nounwind {
; AVX1-LABEL: splatconstant_funnnel_v32i8:
; AVX1: # %bb.0:
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; AVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
-; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2
-; AVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm1
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm3
+; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
+; AVX1-NEXT: vbroadcastss {{.*#+}} ymm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
+; AVX1-NEXT: vandnps %ymm1, %ymm3, %ymm1
; AVX1-NEXT: vpsllw $4, %xmm0, %xmm0
-; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
-; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1-NEXT: vpsllw $4, %xmm2, %xmm2
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: vandps %ymm3, %ymm0, %ymm0
+; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: splatconstant_funnnel_v32i8:
diff --git a/llvm/test/CodeGen/X86/vector-fshr-256.ll b/llvm/test/CodeGen/X86/vector-fshr-256.ll
index 1741ae213d126..6d7d279a3637a 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-256.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-256.ll
@@ -1625,17 +1625,6 @@ define <32 x i8> @constant_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
; AVX1-NEXT: vpmullw %xmm6, %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpackuswb %xmm4, %xmm2, %xmm2
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
-; AVX1-NEXT: vpaddb %xmm4, %xmm4, %xmm4
-; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm7 = [128,32,8,2,128,2,8,32]
-; AVX1-NEXT: vpmaddubsw %xmm7, %xmm4, %xmm8
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm9 = [255,255,255,255,255,255,255,255]
-; AVX1-NEXT: vpand %xmm9, %xmm8, %xmm8
-; AVX1-NEXT: vmovdqa {{.*#+}} xmm10 = [0,64,0,16,0,4,0,1,0,1,0,4,0,16,0,64]
-; AVX1-NEXT: vpmaddubsw %xmm10, %xmm4, %xmm4
-; AVX1-NEXT: vpsllw $8, %xmm4, %xmm4
-; AVX1-NEXT: vpor %xmm4, %xmm8, %xmm4
-; AVX1-NEXT: vpor %xmm2, %xmm4, %xmm2
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm1[8],xmm3[8],xmm1[9],xmm3[9],xmm1[10],xmm3[10],xmm1[11],xmm3[11],xmm1[12],xmm3[12],xmm1[13],xmm3[13],xmm1[14],xmm3[14],xmm1[15],xmm3[15]
; AVX1-NEXT: vpmullw %xmm5, %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
@@ -1643,14 +1632,23 @@ define <32 x i8> @constant_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
; AVX1-NEXT: vpmullw %xmm6, %xmm1, %xmm1
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
; AVX1-NEXT: vpackuswb %xmm3, %xmm1, %xmm1
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm2
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,64,0,16,0,4,0,1,0,1,0,4,0,16,0,64]
+; AVX1-NEXT: vpmaddubsw %xmm3, %xmm2, %xmm4
+; AVX1-NEXT: vpsllw $8, %xmm4, %xmm4
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0
-; AVX1-NEXT: vpmaddubsw %xmm7, %xmm0, %xmm3
-; AVX1-NEXT: vpand %xmm3, %xmm9, %xmm3
-; AVX1-NEXT: vpmaddubsw %xmm10, %xmm0, %xmm0
-; AVX1-NEXT: vpsllw $8, %xmm0, %xmm0
-; AVX1-NEXT: vpor %xmm0, %xmm3, %xmm0
-; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: vpmaddubsw %xmm3, %xmm0, %xmm3
+; AVX1-NEXT: vpsllw $8, %xmm3, %xmm3
+; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm4, %ymm3
+; AVX1-NEXT: vorps %ymm1, %ymm3, %ymm1
+; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm3 = [128,32,8,2,128,2,8,32]
+; AVX1-NEXT: vpmaddubsw %xmm3, %xmm0, %xmm0
+; AVX1-NEXT: vpmaddubsw %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: constant_funnnel_v32i8:
@@ -2058,20 +2056,16 @@ define <16 x i16> @splatconstant_funnnel_v16i16(<16 x i16> %x, <16 x i16> %y) no
define <32 x i8> @splatconstant_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
; AVX1-LABEL: splatconstant_funnnel_v32i8:
; AVX1: # %bb.0:
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
-; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm2
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
-; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
-; AVX1-NEXT: vpsllw $4, %xmm2, %xmm2
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX1-NEXT: vpsllw $4, %xmm0, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpsllw $4, %xmm0, %xmm0
-; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
+; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
diff --git a/llvm/test/CodeGen/X86/vector-fshr-rot-256.ll b/llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
index 3055663786740..c66a3f709c5ca 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
@@ -1674,19 +1674,17 @@ define <16 x i16> @splatconstant_funnnel_v16i16(<16 x i16> %x) nounwind {
define <32 x i8> @splatconstant_funnnel_v32i8(<32 x i8> %x) nounwind {
; AVX1-LABEL: splatconstant_funnnel_v32i8:
; AVX1: # %bb.0:
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm2
-; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
-; AVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
-; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
-; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
-; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
-; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm2
-; AVX1-NEXT: vpandn %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm1
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vpsrlw $4, %xmm2, %xmm3
+; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
+; AVX1-NEXT: vbroadcastss {{.*#+}} ymm3 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
+; AVX1-NEXT: vandnps %ymm1, %ymm3, %ymm1
; AVX1-NEXT: vpsllw $4, %xm...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/130645
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