[llvm] [InstCombine] Fold fneg/fabs patterns with ppc_f128 (PR #130557)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 10 07:43:41 PDT 2025
https://github.com/dtcxzyw updated https://github.com/llvm/llvm-project/pull/130557
>From c087ddd28becf83d182d4c31df79c9cff1554e72 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Mon, 10 Mar 2025 00:19:58 +0800
Subject: [PATCH 1/2] [InstCombine] Fold fneg/fabs patterns with ppc_f128
---
.../InstCombine/InstCombineAndOrXor.cpp | 35 +++++++------------
.../Transforms/InstCombine/fabs-as-int.ll | 4 +--
.../Transforms/InstCombine/fneg-as-int.ll | 4 +--
.../InstCombine/fneg-fabs-as-int.ll | 5 +--
4 files changed, 20 insertions(+), 28 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index 6cc241781d112..8394cbb5e3183 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -2637,18 +2637,15 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) {
// This is a generous interpretation for noimplicitfloat, this is not a true
// floating-point operation.
//
- // Assumes any IEEE-represented type has the sign bit in the high bit.
+ // Assumes any floating point type has the sign bit in the high bit.
// TODO: Unify with APInt matcher. This version allows undef unlike m_APInt
Value *CastOp;
if (match(Op0, m_ElementWiseBitCast(m_Value(CastOp))) &&
- match(Op1, m_MaxSignedValue()) &&
+ CastOp->getType()->isFPOrFPVectorTy() && match(Op1, m_MaxSignedValue()) &&
!Builder.GetInsertBlock()->getParent()->hasFnAttribute(
Attribute::NoImplicitFloat)) {
- Type *EltTy = CastOp->getType()->getScalarType();
- if (EltTy->isFloatingPointTy() && EltTy->isIEEE()) {
- Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, CastOp);
- return new BitCastInst(FAbs, I.getType());
- }
+ Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, CastOp);
+ return new BitCastInst(FAbs, I.getType());
}
// and(shl(zext(X), Y), SignMask) -> and(sext(X), SignMask)
@@ -4047,21 +4044,18 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) {
// the number of instructions. This is still probably a better canonical form
// as it enables FP value tracking.
//
- // Assumes any IEEE-represented type has the sign bit in the high bit.
+ // Assumes any floating point type has the sign bit in the high bit.
//
// This is generous interpretation of noimplicitfloat, this is not a true
// floating-point operation.
Value *CastOp;
if (match(Op0, m_ElementWiseBitCast(m_Value(CastOp))) &&
- match(Op1, m_SignMask()) &&
+ CastOp->getType()->isFPOrFPVectorTy() && match(Op1, m_SignMask()) &&
!Builder.GetInsertBlock()->getParent()->hasFnAttribute(
Attribute::NoImplicitFloat)) {
- Type *EltTy = CastOp->getType()->getScalarType();
- if (EltTy->isFloatingPointTy() && EltTy->isIEEE()) {
- Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, CastOp);
- Value *FNegFAbs = Builder.CreateFNeg(FAbs);
- return new BitCastInst(FNegFAbs, I.getType());
- }
+ Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, CastOp);
+ Value *FNegFAbs = Builder.CreateFNeg(FAbs);
+ return new BitCastInst(FNegFAbs, I.getType());
}
// (X & C1) | C2 -> X & (C1 | C2) iff (X & C2) == C2
@@ -4851,18 +4845,15 @@ Instruction *InstCombinerImpl::visitXor(BinaryOperator &I) {
// This is generous interpretation of noimplicitfloat, this is not a true
// floating-point operation.
//
- // Assumes any IEEE-represented type has the sign bit in the high bit.
+ // Assumes any floating point type has the sign bit in the high bit.
// TODO: Unify with APInt matcher. This version allows undef unlike m_APInt
Value *CastOp;
if (match(Op0, m_ElementWiseBitCast(m_Value(CastOp))) &&
- match(Op1, m_SignMask()) &&
+ CastOp->getType()->isFPOrFPVectorTy() && match(Op1, m_SignMask()) &&
!Builder.GetInsertBlock()->getParent()->hasFnAttribute(
Attribute::NoImplicitFloat)) {
- Type *EltTy = CastOp->getType()->getScalarType();
- if (EltTy->isFloatingPointTy() && EltTy->isIEEE()) {
- Value *FNeg = Builder.CreateFNeg(CastOp);
- return new BitCastInst(FNeg, I.getType());
- }
+ Value *FNeg = Builder.CreateFNeg(CastOp);
+ return new BitCastInst(FNeg, I.getType());
}
}
diff --git a/llvm/test/Transforms/InstCombine/fabs-as-int.ll b/llvm/test/Transforms/InstCombine/fabs-as-int.ll
index 9d28cae8f04d6..f0e83ca6302fe 100644
--- a/llvm/test/Transforms/InstCombine/fabs-as-int.ll
+++ b/llvm/test/Transforms/InstCombine/fabs-as-int.ll
@@ -289,8 +289,8 @@ define i128 @fabs_as_int_ppc_fp128_f64_mask(ppc_fp128 %x) {
define i128 @fabs_as_int_ppc_fp128_f128_mask(ppc_fp128 %x) {
; CHECK-LABEL: define i128 @fabs_as_int_ppc_fp128_f128_mask
; CHECK-SAME: (ppc_fp128 [[X:%.*]]) {
-; CHECK-NEXT: [[BC:%.*]] = bitcast ppc_fp128 [[X]] to i128
-; CHECK-NEXT: [[AND:%.*]] = and i128 [[BC]], 170141183460469231731687303715884105727
+; CHECK-NEXT: [[TMP1:%.*]] = call ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128 [[X]])
+; CHECK-NEXT: [[AND:%.*]] = bitcast ppc_fp128 [[TMP1]] to i128
; CHECK-NEXT: ret i128 [[AND]]
;
%bc = bitcast ppc_fp128 %x to i128
diff --git a/llvm/test/Transforms/InstCombine/fneg-as-int.ll b/llvm/test/Transforms/InstCombine/fneg-as-int.ll
index f8d88b4f238f2..590aca687e5b5 100644
--- a/llvm/test/Transforms/InstCombine/fneg-as-int.ll
+++ b/llvm/test/Transforms/InstCombine/fneg-as-int.ll
@@ -291,8 +291,8 @@ define i128 @fneg_as_int_ppc_fp128_f64_mask(ppc_fp128 %x) {
define i128 @fneg_as_int_ppc_fp128_f128_mask(ppc_fp128 %x) {
; CHECK-LABEL: define i128 @fneg_as_int_ppc_fp128_f128_mask
; CHECK-SAME: (ppc_fp128 [[X:%.*]]) {
-; CHECK-NEXT: [[BC:%.*]] = bitcast ppc_fp128 [[X]] to i128
-; CHECK-NEXT: [[XOR:%.*]] = xor i128 [[BC]], -170141183460469231731687303715884105728
+; CHECK-NEXT: [[TMP1:%.*]] = fneg ppc_fp128 [[X]]
+; CHECK-NEXT: [[XOR:%.*]] = bitcast ppc_fp128 [[TMP1]] to i128
; CHECK-NEXT: ret i128 [[XOR]]
;
%bc = bitcast ppc_fp128 %x to i128
diff --git a/llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll b/llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll
index 8b245bdd79299..a0894c3febc94 100644
--- a/llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll
+++ b/llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll
@@ -317,8 +317,9 @@ define i128 @fneg_fabs_as_int_ppc_fp128_f64_mask(ppc_fp128 %x) {
define i128 @fneg_fabs_as_int_ppc_fp128_f128_mask(ppc_fp128 %x) {
; CHECK-LABEL: define i128 @fneg_fabs_as_int_ppc_fp128_f128_mask
; CHECK-SAME: (ppc_fp128 [[X:%.*]]) {
-; CHECK-NEXT: [[BC:%.*]] = bitcast ppc_fp128 [[X]] to i128
-; CHECK-NEXT: [[OR:%.*]] = or i128 [[BC]], -170141183460469231731687303715884105728
+; CHECK-NEXT: [[TMP1:%.*]] = call ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128 [[X]])
+; CHECK-NEXT: [[TMP2:%.*]] = fneg ppc_fp128 [[TMP1]]
+; CHECK-NEXT: [[OR:%.*]] = bitcast ppc_fp128 [[TMP2]] to i128
; CHECK-NEXT: ret i128 [[OR]]
;
%bc = bitcast ppc_fp128 %x to i128
>From 029da63644299196703e466390a9aa7e8abadf77 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Mon, 10 Mar 2025 21:04:58 +0800
Subject: [PATCH 2/2] [ADT] Add `hasSignBitInMSB` helper
---
llvm/include/llvm/ADT/APFloat.h | 1 +
llvm/lib/Support/APFloat.cpp | 19 ++++++++++++++++---
.../InstCombine/InstCombineAndOrXor.cpp | 15 ++++++++++++---
llvm/unittests/ADT/APFloatTest.cpp | 6 ++++++
4 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index 00d92740259eb..40fad7cb62271 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -354,6 +354,7 @@ struct APFloatBase {
static bool semanticsHasInf(const fltSemantics &);
static bool semanticsHasNaN(const fltSemantics &);
static bool isIEEELikeFP(const fltSemantics &);
+ static bool hasSignBitInMSB(const fltSemantics &);
// Returns true if any number described by \p Src can be precisely represented
// by a normal (not subnormal) value in \p Dst.
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index cfc3c3b4974c5..32e83eef77164 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -125,6 +125,9 @@ struct fltSemantics {
/* Whether this semantics can represent signed values */
bool hasSignedRepr = true;
+
+ /* Whether the sign bit of this semantics is the most significant bit */
+ bool hasSignBitInMSB = true;
};
static constexpr fltSemantics semIEEEhalf = {15, -14, 11, 16};
@@ -144,9 +147,15 @@ static constexpr fltSemantics semFloat8E4M3B11FNUZ = {
4, -10, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::NegativeZero};
static constexpr fltSemantics semFloat8E3M4 = {3, -2, 5, 8};
static constexpr fltSemantics semFloatTF32 = {127, -126, 11, 19};
-static constexpr fltSemantics semFloat8E8M0FNU = {
- 127, -127, 1, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::AllOnes,
- false, false};
+static constexpr fltSemantics semFloat8E8M0FNU = {127,
+ -127,
+ 1,
+ 8,
+ fltNonfiniteBehavior::NanOnly,
+ fltNanEncoding::AllOnes,
+ false,
+ false,
+ false};
static constexpr fltSemantics semFloat6E3M2FN = {
4, -2, 3, 6, fltNonfiniteBehavior::FiniteOnly};
@@ -358,6 +367,10 @@ bool APFloatBase::isIEEELikeFP(const fltSemantics &semantics) {
return SemanticsToEnum(semantics) <= S_IEEEquad;
}
+bool APFloatBase::hasSignBitInMSB(const fltSemantics &semantics) {
+ return semantics.hasSignBitInMSB;
+}
+
bool APFloatBase::isRepresentableAsNormalIn(const fltSemantics &Src,
const fltSemantics &Dst) {
// Exponent range must be larger.
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index 8394cbb5e3183..ee888eaaf7c2b 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -2641,7 +2641,10 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) {
// TODO: Unify with APInt matcher. This version allows undef unlike m_APInt
Value *CastOp;
if (match(Op0, m_ElementWiseBitCast(m_Value(CastOp))) &&
- CastOp->getType()->isFPOrFPVectorTy() && match(Op1, m_MaxSignedValue()) &&
+ CastOp->getType()->isFPOrFPVectorTy() &&
+ APFloat::hasSignBitInMSB(
+ CastOp->getType()->getScalarType()->getFltSemantics()) &&
+ match(Op1, m_MaxSignedValue()) &&
!Builder.GetInsertBlock()->getParent()->hasFnAttribute(
Attribute::NoImplicitFloat)) {
Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, CastOp);
@@ -4050,7 +4053,10 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) {
// floating-point operation.
Value *CastOp;
if (match(Op0, m_ElementWiseBitCast(m_Value(CastOp))) &&
- CastOp->getType()->isFPOrFPVectorTy() && match(Op1, m_SignMask()) &&
+ CastOp->getType()->isFPOrFPVectorTy() &&
+ APFloat::hasSignBitInMSB(
+ CastOp->getType()->getScalarType()->getFltSemantics()) &&
+ match(Op1, m_SignMask()) &&
!Builder.GetInsertBlock()->getParent()->hasFnAttribute(
Attribute::NoImplicitFloat)) {
Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, CastOp);
@@ -4849,7 +4855,10 @@ Instruction *InstCombinerImpl::visitXor(BinaryOperator &I) {
// TODO: Unify with APInt matcher. This version allows undef unlike m_APInt
Value *CastOp;
if (match(Op0, m_ElementWiseBitCast(m_Value(CastOp))) &&
- CastOp->getType()->isFPOrFPVectorTy() && match(Op1, m_SignMask()) &&
+ CastOp->getType()->isFPOrFPVectorTy() &&
+ APFloat::hasSignBitInMSB(
+ CastOp->getType()->getScalarType()->getFltSemantics()) &&
+ match(Op1, m_SignMask()) &&
!Builder.GetInsertBlock()->getParent()->hasFnAttribute(
Attribute::NoImplicitFloat)) {
Value *FNeg = Builder.CreateFNeg(CastOp);
diff --git a/llvm/unittests/ADT/APFloatTest.cpp b/llvm/unittests/ADT/APFloatTest.cpp
index c2d99f3312b88..00eab5d9dc514 100644
--- a/llvm/unittests/ADT/APFloatTest.cpp
+++ b/llvm/unittests/ADT/APFloatTest.cpp
@@ -8168,4 +8168,10 @@ TEST(APFloatTest, Float4E2M1FNToFloat) {
EXPECT_TRUE(SmallestDenorm.isDenormal());
EXPECT_EQ(0x0.8p0, SmallestDenorm.convertToFloat());
}
+
+TEST(APFloatTest, hasSignBitInMSB) {
+ EXPECT_TRUE(APFloat::hasSignBitInMSB(APFloat::IEEEsingle()));
+ EXPECT_FALSE(APFloat::hasSignBitInMSB(APFloat::Float8E8M0FNU()));
+}
+
} // namespace
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