[llvm] 5d92171 - [X86] combineConcatVectorOps - convert X86ISD::HADD/SUB concatenation to use combineConcatVectorOps recursion (#130579)
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Mon Mar 10 06:03:30 PDT 2025
Author: Simon Pilgrim
Date: 2025-03-10T13:03:27Z
New Revision: 5d921710c0d6984950f74ba57192aed9c67a84f3
URL: https://github.com/llvm/llvm-project/commit/5d921710c0d6984950f74ba57192aed9c67a84f3
DIFF: https://github.com/llvm/llvm-project/commit/5d921710c0d6984950f74ba57192aed9c67a84f3.diff
LOG: [X86] combineConcatVectorOps - convert X86ISD::HADD/SUB concatenation to use combineConcatVectorOps recursion (#130579)
Only concatenate X86ISD::HADD/SUB nodes if at least one operand is beneficial to concatenate
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/haddsub-undef.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index ccd7f2418fcd1..ed7f491071ec4 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -58419,9 +58419,12 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
case X86ISD::FHSUB:
if (!IsSplat && VT.is256BitVector() &&
(VT.isFloatingPoint() || Subtarget.hasInt256())) {
- return DAG.getNode(Op0.getOpcode(), DL, VT,
- ConcatSubOperand(VT, Ops, 0),
- ConcatSubOperand(VT, Ops, 1));
+ SDValue Concat0 = CombineSubOperand(VT, Ops, 0);
+ SDValue Concat1 = CombineSubOperand(VT, Ops, 1);
+ if (Concat0 || Concat1)
+ return DAG.getNode(Op0.getOpcode(), DL, VT,
+ Concat0 ? Concat0 : ConcatSubOperand(VT, Ops, 0),
+ Concat1 ? Concat1 : ConcatSubOperand(VT, Ops, 1));
}
break;
case X86ISD::PACKSS:
diff --git a/llvm/test/CodeGen/X86/haddsub-undef.ll b/llvm/test/CodeGen/X86/haddsub-undef.ll
index 6aa53278d81ef..94fa81742ba71 100644
--- a/llvm/test/CodeGen/X86/haddsub-undef.ll
+++ b/llvm/test/CodeGen/X86/haddsub-undef.ll
@@ -694,9 +694,9 @@ define <4 x double> @add_pd_011(<4 x double> %0, <4 x double> %1) {
;
; AVX1-FAST-LABEL: add_pd_011:
; AVX1-FAST: # %bb.0:
-; AVX1-FAST-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm2
-; AVX1-FAST-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX1-FAST-NEXT: vhaddpd %ymm2, %ymm0, %ymm0
+; AVX1-FAST-NEXT: vhaddpd %xmm0, %xmm1, %xmm2
+; AVX1-FAST-NEXT: vhaddpd %xmm1, %xmm0, %xmm0
+; AVX1-FAST-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-FAST-NEXT: retq
;
; AVX512-LABEL: add_pd_011:
@@ -1272,9 +1272,9 @@ define <4 x double> @PR34724_add_v4f64_012u(<4 x double> %0, <4 x double> %1) {
; AVX-FAST-LABEL: PR34724_add_v4f64_012u:
; AVX-FAST: # %bb.0:
; AVX-FAST-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX-FAST-NEXT: vhaddpd %xmm2, %xmm0, %xmm0
+; AVX-FAST-NEXT: vhaddpd %xmm1, %xmm1, %xmm1
; AVX-FAST-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; AVX-FAST-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
-; AVX-FAST-NEXT: vhaddpd %ymm1, %ymm0, %ymm0
; AVX-FAST-NEXT: retq
%3 = shufflevector <4 x double> %0, <4 x double> undef, <2 x i32> <i32 0, i32 2>
%4 = shufflevector <4 x double> %0, <4 x double> undef, <2 x i32> <i32 1, i32 3>
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