[llvm] [AMDGPU][NPM] Support -regalloc-npm options (PR #129035)
Akshat Oke via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 10 01:16:20 PDT 2025
https://github.com/optimisan updated https://github.com/llvm/llvm-project/pull/129035
>From dda0330470f761db7f9db254e05ab7d25d91651c Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Thu, 27 Feb 2025 10:12:06 +0000
Subject: [PATCH 1/4] [AMDGPU][NPM] Support -{phase}-regalloc-npm options
---
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 227 ++++++++++++++++++
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 35 +++
2 files changed, 262 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index ce3dcd920bce3..dd8e04fcd91f1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -77,6 +77,7 @@
#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/RegAllocFast.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
@@ -188,6 +189,24 @@ static cl::opt<WWMRegisterRegAlloc::FunctionPassCtor, false,
cl::init(&useDefaultRegisterAllocator),
cl::desc("Register allocator to use for WWM registers"));
+static cl::opt<RegAllocType, false, RegAllocTypeParser> SGPRRegAllocTypeNPM(
+ "sgpr-regalloc-npm", cl::Hidden,
+ cl::desc("Register allocator to use for SGPRs in new pass "
+ "manager"),
+ cl::init(RegAllocType::Default));
+
+static cl::opt<RegAllocType, false, RegAllocTypeParser> VGPRRegAllocTypeNPM(
+ "vgpr-regalloc-npm", cl::Hidden,
+ cl::desc("Register allocator to use for VGPRs in new pass "
+ "manager"),
+ cl::init(RegAllocType::Default));
+
+static cl::opt<RegAllocType, false, RegAllocTypeParser> WWMRegAllocTypeNPM(
+ "wwm-regalloc-npm", cl::Hidden,
+ cl::desc("Register allocator to use for WWM registers in "
+ "new pass manager"),
+ cl::init(RegAllocType::Default));
+
static void initializeDefaultSGPRRegisterAllocatorOnce() {
RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
@@ -2140,6 +2159,214 @@ void AMDGPUCodeGenPassBuilder::addMachineSSAOptimization(
addPass(SIShrinkInstructionsPass());
}
+static const char NPMRegAllocOptNotSupportedMessage[] =
+ "-regalloc-npm not supported with amdgcn. Use -sgpr-regalloc-npm, "
+ "-wwm-regalloc-npm, "
+ "and -vgpr-regalloc-npm";
+
+// void AMDGPUCodeGenPassBuilder::addSGPRRegAlloc(AddMachinePass &addPass,
+// RegAllocType RAType, RegAllocFilterFunc FilterFunc, bool Optimized) const {
+// RegAllocType RAType = RegAllocTypeNPM;
+// if (RAType == RegAllocType::Default) {
+// RAType = Optimized ? RegAllocType::Greedy : RegAllocType::Fast;
+// }
+
+// if (RAType == RegAllocType::Greedy) {
+// addPass(RAGreedyPass({onlyAllocateSGPRs, "sgpr"}));
+// return;
+// }
+
+// if (RAType == RegAllocType::Fast) {
+// addPass(RegAllocFastPass({onlyAllocateSGPRs, "sgpr", false}));
+// return;
+// }
+// report_fatal_error("Unsupported SGPR regalloc type", false);
+// }
+
+// template<typename RegAllocPass>
+// void AMDGPUCodeGenPassBuilder::addRegAllocOfType(AddMachinePass &addPass,
+// RegAllocPass::Options Options) {
+// addPass(RegAllocPass(Options));
+// }
+
+// this is the final method
+// template<typename RegAllocPass>
+// void AMDGPUCodeGenPassBuilder::addRegAllocOfType(AddMachinePass &addPass,
+// RegAllocPhase Phase) {
+// #define RA_OPTIONS(FilterFunc, Name, ClearVirtRegs) \
+// [&]() { \
+// if constexpr (std::is_same_v<RegAllocPass, RegAllocFastPass>) { \
+// return RegAllocFastPass::Options{FilterFunc, Name, ClearVirtRegs}; \
+// } else { \
+// return typename RegAllocPass::Options{FilterFunc, Name}; \
+// } \
+// }()
+
+// typename RegAllocPass::Options Options;
+// RegAllocType RAType;
+
+// switch (Phase) {
+// case RegAllocPhase::SGPR:
+// Options = RA_OPTIONS(onlyAllocateSGPRs, "sgpr", false);
+// RAType = SGPRRegAllocTypeNPM;
+// break;
+// case RegAllocPhase::WWM:
+// Options = RA_OPTIONS(onlyAllocateWWMRegs, "wwm", false);
+// RAType = WWMRegAllocTypeNPM;
+// break;
+// case RegAllocPhase::VGPR:
+// Options = RA_OPTIONS(onlyAllocateVGPRs, "vgpr", true);
+// RAType = VGPRRegAllocTypeNPM;
+// break;
+// };
+
+// switch(RAType) {
+// case RegAllocType::Greedy:
+// addPass(RAGreedyPass(Options));
+// return;
+// case RegAllocType::Fast:
+// addPass(RegAllocFastPass(Options));
+// return;
+// case RegAllocType::Unset:
+// addPass(RegAllocPass(Options));
+// }
+// #undef RA_OPTIONS
+// }
+
+// template<typename RegAllocPass>
+// void AMDGPUCodeGenPassBuilder::addRegAlloc(AddMachinePass &addPass,
+// RegAllocPhase Phase) {
+// RegAllocType RAType;
+// switch(Phase) {
+// case RegAllocPhase::SGPR:
+// RAType = SGPRRegAllocTypeNPM;
+// break;
+// case RegAllocPhase::WWM:
+// RAType = WWMRegAllocTypeNPM;
+// break;
+// case RegAllocPhase::VGPR:
+// RAType = VGPRRegAllocTypeNPM;
+// break;
+// }
+// switch (RAType) {
+// case RegAllocType::Greedy:
+// addRegAllocOfType(addPass, Phase);
+// }
+// addRegAllocOfType<RegAllocPass>(addPass, Phase);
+// }
+
+template <typename RegAllocPassT>
+typename RegAllocPassT::Options
+AMDGPUCodeGenPassBuilder::getRAOptionsForPhase(RegAllocPhase Phase) const {
+#define RA_OPTIONS(FilterFunc, Name, ClearVirtRegs) \
+ [&]() { \
+ if constexpr (std::is_same_v<RegAllocPassT, RegAllocFastPass>) { \
+ return RegAllocFastPass::Options{FilterFunc, Name, ClearVirtRegs}; \
+ } else { \
+ return typename RegAllocPassT::Options{FilterFunc, Name}; \
+ } \
+ }()
+
+ switch (Phase) {
+ case RegAllocPhase::SGPR:
+ return RA_OPTIONS(onlyAllocateSGPRs, "sgpr", false);
+ case RegAllocPhase::WWM:
+ return RA_OPTIONS(onlyAllocateWWMRegs, "wwm", false);
+ case RegAllocPhase::VGPR:
+ return RA_OPTIONS(onlyAllocateVGPRs, "vgpr", true);
+ }
+ // static_assert(std::is_same_v<PhaseT, SGPRPhase> ||
+ // std::is_same_v<PhaseT, WWMPhase> ||
+ // std::is_same_v<PhaseT, VGPRPhase>,
+ // "Unsupported phase type");
+
+ // if constexpr(std::is_same_v<PhaseT, SGPRPhase>) {
+ // return RA_OPTIONS(onlyAllocateSGPRs, "sgpr", false);
+ // } else if constexpr(std::is_same_v<PhaseT, WWMPhase>) {
+ // return RA_OPTIONS(onlyAllocateWWMRegs, "wwm", false);
+ // } else if constexpr(std::is_same_v<PhaseT, VGPRPhase>) {
+ // return RA_OPTIONS(onlyAllocateVGPRs, "vgpr", true);
+ // }
+
+#undef RA_OPTIONS
+}
+
+template <typename RegAllocPassT>
+void AMDGPUCodeGenPassBuilder::addRegAlloc(AddMachinePass &addPass,
+ RegAllocPhase Phase) const {
+ RegAllocType RAType;
+ // Read the appropriate phase's regalloc type.
+ switch (Phase) {
+ case RegAllocPhase::SGPR:
+ RAType = SGPRRegAllocTypeNPM;
+ break;
+ case RegAllocPhase::WWM:
+ RAType = WWMRegAllocTypeNPM;
+ break;
+ case RegAllocPhase::VGPR:
+ RAType = VGPRRegAllocTypeNPM;
+ break;
+ }
+
+ // Construct the pass with the appropriate options.
+ switch (RAType) {
+ case RegAllocType::Greedy:
+ addPass(RAGreedyPass(getRAOptionsForPhase<RAGreedyPass>(Phase)));
+ return;
+ case RegAllocType::Fast:
+ addPass(RegAllocFastPass(getRAOptionsForPhase<RegAllocFastPass>(Phase)));
+ return;
+ case RegAllocType::Unset:
+ addPass(RegAllocPassT(getRAOptionsForPhase<RegAllocPassT>(Phase)));
+ return;
+ default:
+ report_fatal_error("Unsupported regalloc type", false);
+ }
+}
+
+Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized(
+ AddMachinePass &addPass) const {
+ if (Opt.RegAlloc != RegAllocType::Unset)
+ return make_error<StringError>(NPMRegAllocOptNotSupportedMessage,
+ inconvertibleErrorCode());
+
+ addPass(GCNPreRALongBranchRegPass());
+
+ addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::SGPR);
+
+ // Commit allocated register changes. This is mostly necessary because too
+ // many things rely on the use lists of the physical registers, such as the
+ // verifier. This is only necessary with allocators which use LiveIntervals,
+ // since FastRegAlloc does the replacements itself.
+ // TODO: addPass(VirtRegRewriterPass(false));
+
+ // At this point, the sgpr-regalloc has been done and it is good to have the
+ // stack slot coloring to try to optimize the SGPR spill stack indices before
+ // attempting the custom SGPR spill lowering.
+ addPass(StackSlotColoringPass());
+
+ // Equivalent of PEI for SGPRs.
+ addPass(SILowerSGPRSpillsPass());
+
+ // To Allocate wwm registers used in whole quad mode operations (for shaders).
+ addPass(SIPreAllocateWWMRegsPass());
+
+ // For allocating other wwm register operands.
+ addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::WWM);
+ addPass(SILowerWWMCopiesPass());
+ // TODO: addPass(VirtRegRewriterPass(false));
+ // TODO: addPass(AMDGPUReserveWWMRegsPass());
+
+ // For allocating per-thread VGPRs.
+ addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::VGPR);
+
+ // TODO: addPreRewrite();
+ addPass(VirtRegRewriterPass(false));
+
+ // TODO: addPass(AMDGPUMarkLastScratchLoadPass());
+ return Error::success();
+}
+
void AMDGPUCodeGenPassBuilder::addPostRegAlloc(AddMachinePass &addPass) const {
addPass(SIFixVGPRCopiesPass());
if (TM.getOptLevel() > CodeGenOptLevel::None)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index 3df4115324ac2..dffb53be44d4d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -16,9 +16,11 @@
#include "GCNSubtarget.h"
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
+#include "llvm/CodeGen/RegAllocCommon.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Passes/CodeGenPassBuilder.h"
+#include "llvm/Target/CGPassBuilderOption.h"
#include <optional>
#include <utility>
@@ -179,6 +181,7 @@ class AMDGPUCodeGenPassBuilder
Error addInstSelector(AddMachinePass &) const;
void addPreRewrite(AddMachinePass &) const;
void addMachineSSAOptimization(AddMachinePass &) const;
+ Error addRegAssignmentOptimized(AddMachinePass &) const;
void addPostRegAlloc(AddMachinePass &) const;
void addPreEmitPass(AddMachinePass &) const;
@@ -189,6 +192,38 @@ class AMDGPUCodeGenPassBuilder
CodeGenOptLevel Level = CodeGenOptLevel::Default) const;
void addEarlyCSEOrGVNPass(AddIRPass &) const;
void addStraightLineScalarOptimizationPasses(AddIRPass &) const;
+
+private:
+ // /// Dummy structs to represent different phases of register allocation.
+ // struct SGPRPhase{};
+ // struct VGPRPhase{};
+ // struct WWMPhase{};
+ enum class RegAllocPhase { SGPR, VGPR, WWM };
+
+ template <typename RegAllocPassT>
+ typename RegAllocPassT::Options getRAOptionsForPhase(RegAllocPhase) const;
+
+ /// \brief Add register allocation pass to the pass manager.
+ /// This checks for the regalloc type given through
+ /// -{phase}-regalloc-npm={type} cl option. If the option is not specified, it
+ /// uses the preferred regalloc pass type.
+ ///
+ /// \tparam PreferredRegAllocPassT The fallback reg alloc pass type to use if
+ /// cl::opt is unspecified.
+ /// \param Phase The phase of register allocation to add.
+ template <typename PreferredRegAllocPassT>
+ void addRegAlloc(AddMachinePass &, RegAllocPhase Phase) const;
+
+ // instantiate the template for each phase
+ /// Add the register allocation pass for given filter func and type
+ /// (greedy/fast).
+ /// @param Type If RegAllocType::Default, add according to the optimization
+ /// level.
+ // void addRegAllocPass(AddMachinePass &, RegAllocType Type,
+ // RegAllocFilterFunc FilterFunc) const;
+ void addSGPRRegAlloc(AddMachinePass &, bool Optimized) const;
+ void addWWMRegAlloc(AddMachinePass &, bool Optimized) const;
+ void addVGPRRegAlloc(AddMachinePass &, bool Optimized) const;
};
} // end namespace llvm
>From 3be94ae918454d73a77f54f3f878742f329144fe Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Thu, 27 Feb 2025 10:33:59 +0000
Subject: [PATCH 2/4] add test
---
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 106 +-----------------
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 4 -
.../test/tools/llc/new-pm/regalloc-amdgpu.mir | 5 +
3 files changed, 7 insertions(+), 108 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index dd8e04fcd91f1..fee430b005475 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -2164,97 +2164,6 @@ static const char NPMRegAllocOptNotSupportedMessage[] =
"-wwm-regalloc-npm, "
"and -vgpr-regalloc-npm";
-// void AMDGPUCodeGenPassBuilder::addSGPRRegAlloc(AddMachinePass &addPass,
-// RegAllocType RAType, RegAllocFilterFunc FilterFunc, bool Optimized) const {
-// RegAllocType RAType = RegAllocTypeNPM;
-// if (RAType == RegAllocType::Default) {
-// RAType = Optimized ? RegAllocType::Greedy : RegAllocType::Fast;
-// }
-
-// if (RAType == RegAllocType::Greedy) {
-// addPass(RAGreedyPass({onlyAllocateSGPRs, "sgpr"}));
-// return;
-// }
-
-// if (RAType == RegAllocType::Fast) {
-// addPass(RegAllocFastPass({onlyAllocateSGPRs, "sgpr", false}));
-// return;
-// }
-// report_fatal_error("Unsupported SGPR regalloc type", false);
-// }
-
-// template<typename RegAllocPass>
-// void AMDGPUCodeGenPassBuilder::addRegAllocOfType(AddMachinePass &addPass,
-// RegAllocPass::Options Options) {
-// addPass(RegAllocPass(Options));
-// }
-
-// this is the final method
-// template<typename RegAllocPass>
-// void AMDGPUCodeGenPassBuilder::addRegAllocOfType(AddMachinePass &addPass,
-// RegAllocPhase Phase) {
-// #define RA_OPTIONS(FilterFunc, Name, ClearVirtRegs) \
-// [&]() { \
-// if constexpr (std::is_same_v<RegAllocPass, RegAllocFastPass>) { \
-// return RegAllocFastPass::Options{FilterFunc, Name, ClearVirtRegs}; \
-// } else { \
-// return typename RegAllocPass::Options{FilterFunc, Name}; \
-// } \
-// }()
-
-// typename RegAllocPass::Options Options;
-// RegAllocType RAType;
-
-// switch (Phase) {
-// case RegAllocPhase::SGPR:
-// Options = RA_OPTIONS(onlyAllocateSGPRs, "sgpr", false);
-// RAType = SGPRRegAllocTypeNPM;
-// break;
-// case RegAllocPhase::WWM:
-// Options = RA_OPTIONS(onlyAllocateWWMRegs, "wwm", false);
-// RAType = WWMRegAllocTypeNPM;
-// break;
-// case RegAllocPhase::VGPR:
-// Options = RA_OPTIONS(onlyAllocateVGPRs, "vgpr", true);
-// RAType = VGPRRegAllocTypeNPM;
-// break;
-// };
-
-// switch(RAType) {
-// case RegAllocType::Greedy:
-// addPass(RAGreedyPass(Options));
-// return;
-// case RegAllocType::Fast:
-// addPass(RegAllocFastPass(Options));
-// return;
-// case RegAllocType::Unset:
-// addPass(RegAllocPass(Options));
-// }
-// #undef RA_OPTIONS
-// }
-
-// template<typename RegAllocPass>
-// void AMDGPUCodeGenPassBuilder::addRegAlloc(AddMachinePass &addPass,
-// RegAllocPhase Phase) {
-// RegAllocType RAType;
-// switch(Phase) {
-// case RegAllocPhase::SGPR:
-// RAType = SGPRRegAllocTypeNPM;
-// break;
-// case RegAllocPhase::WWM:
-// RAType = WWMRegAllocTypeNPM;
-// break;
-// case RegAllocPhase::VGPR:
-// RAType = VGPRRegAllocTypeNPM;
-// break;
-// }
-// switch (RAType) {
-// case RegAllocType::Greedy:
-// addRegAllocOfType(addPass, Phase);
-// }
-// addRegAllocOfType<RegAllocPass>(addPass, Phase);
-// }
-
template <typename RegAllocPassT>
typename RegAllocPassT::Options
AMDGPUCodeGenPassBuilder::getRAOptionsForPhase(RegAllocPhase Phase) const {
@@ -2275,18 +2184,6 @@ AMDGPUCodeGenPassBuilder::getRAOptionsForPhase(RegAllocPhase Phase) const {
case RegAllocPhase::VGPR:
return RA_OPTIONS(onlyAllocateVGPRs, "vgpr", true);
}
- // static_assert(std::is_same_v<PhaseT, SGPRPhase> ||
- // std::is_same_v<PhaseT, WWMPhase> ||
- // std::is_same_v<PhaseT, VGPRPhase>,
- // "Unsupported phase type");
-
- // if constexpr(std::is_same_v<PhaseT, SGPRPhase>) {
- // return RA_OPTIONS(onlyAllocateSGPRs, "sgpr", false);
- // } else if constexpr(std::is_same_v<PhaseT, WWMPhase>) {
- // return RA_OPTIONS(onlyAllocateWWMRegs, "wwm", false);
- // } else if constexpr(std::is_same_v<PhaseT, VGPRPhase>) {
- // return RA_OPTIONS(onlyAllocateVGPRs, "vgpr", true);
- // }
#undef RA_OPTIONS
}
@@ -2317,10 +2214,11 @@ void AMDGPUCodeGenPassBuilder::addRegAlloc(AddMachinePass &addPass,
addPass(RegAllocFastPass(getRAOptionsForPhase<RegAllocFastPass>(Phase)));
return;
case RegAllocType::Unset:
+ case RegAllocType::Default:
addPass(RegAllocPassT(getRAOptionsForPhase<RegAllocPassT>(Phase)));
return;
default:
- report_fatal_error("Unsupported regalloc type", false);
+ report_fatal_error("Unsupported regalloc type for AMDGPU", false);
}
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index dffb53be44d4d..ab9220d5e978f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -194,10 +194,6 @@ class AMDGPUCodeGenPassBuilder
void addStraightLineScalarOptimizationPasses(AddIRPass &) const;
private:
- // /// Dummy structs to represent different phases of register allocation.
- // struct SGPRPhase{};
- // struct VGPRPhase{};
- // struct WWMPhase{};
enum class RegAllocPhase { SGPR, VGPR, WWM };
template <typename RegAllocPassT>
diff --git a/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir b/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
index 07f2d350ffd9c..2398dc816acc3 100644
--- a/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
+++ b/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
@@ -2,11 +2,16 @@
# RUN: llc -mtriple=amdgcn --passes='regallocfast<filter=sgpr>,regallocfast<filter=wwm>,regallocfast<filter=vgpr>' --print-pipeline-passes --filetype=null %s | FileCheck %s --check-prefix=PASS
# RUN: not llc -mtriple=amdgcn --passes='regallocfast<filter=bad-filter>' --print-pipeline-passes --filetype=null %s 2>&1 | FileCheck %s --check-prefix=BAD-FILTER
+# RUN: llc -mtriple=amdgcn -enable-new-pm -sgpr-regalloc-npm=greedy -vgpr-regalloc-npm=fast -print-pipeline-passes %s | FileCheck %s --check-prefix=NPM-PASS
+
+
# PASS: regallocfast<filter=sgpr>
# PASS: regallocfast<filter=wwm>
# PASS: regallocfast<filter=vgpr>
# BAD-FILTER: invalid regallocfast register filter 'bad-filter'
+# NPM-PASS: greedy<sgpr>
+# NPM-PASS: regallocfast<filter=vgpr>
---
name: f
...
>From ff3ebf3a20b491b7ae913e7b25fd843e7732d19f Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Thu, 27 Feb 2025 10:37:32 +0000
Subject: [PATCH 3/4] cleanup drafts
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index ab9220d5e978f..053d76e89ce08 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -209,17 +209,6 @@ class AMDGPUCodeGenPassBuilder
/// \param Phase The phase of register allocation to add.
template <typename PreferredRegAllocPassT>
void addRegAlloc(AddMachinePass &, RegAllocPhase Phase) const;
-
- // instantiate the template for each phase
- /// Add the register allocation pass for given filter func and type
- /// (greedy/fast).
- /// @param Type If RegAllocType::Default, add according to the optimization
- /// level.
- // void addRegAllocPass(AddMachinePass &, RegAllocType Type,
- // RegAllocFilterFunc FilterFunc) const;
- void addSGPRRegAlloc(AddMachinePass &, bool Optimized) const;
- void addWWMRegAlloc(AddMachinePass &, bool Optimized) const;
- void addVGPRRegAlloc(AddMachinePass &, bool Optimized) const;
};
} // end namespace llvm
>From b85a8efd8f3b49b2d25bb561b01756a1b12bdd3d Mon Sep 17 00:00:00 2001
From: Akshat Oke <Akshat.Oke at amd.com>
Date: Thu, 27 Feb 2025 10:38:58 +0000
Subject: [PATCH 4/4] add wwm flag to the test
---
llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir b/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
index 2398dc816acc3..ca0420ffaea3f 100644
--- a/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
+++ b/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
@@ -2,7 +2,7 @@
# RUN: llc -mtriple=amdgcn --passes='regallocfast<filter=sgpr>,regallocfast<filter=wwm>,regallocfast<filter=vgpr>' --print-pipeline-passes --filetype=null %s | FileCheck %s --check-prefix=PASS
# RUN: not llc -mtriple=amdgcn --passes='regallocfast<filter=bad-filter>' --print-pipeline-passes --filetype=null %s 2>&1 | FileCheck %s --check-prefix=BAD-FILTER
-# RUN: llc -mtriple=amdgcn -enable-new-pm -sgpr-regalloc-npm=greedy -vgpr-regalloc-npm=fast -print-pipeline-passes %s | FileCheck %s --check-prefix=NPM-PASS
+# RUN: llc -mtriple=amdgcn -enable-new-pm -sgpr-regalloc-npm=greedy -wwm-regalloc-npm=fast -vgpr-regalloc-npm=fast -print-pipeline-passes %s | FileCheck %s --check-prefix=NPM-PASS
# PASS: regallocfast<filter=sgpr>
@@ -11,6 +11,7 @@
# BAD-FILTER: invalid regallocfast register filter 'bad-filter'
# NPM-PASS: greedy<sgpr>
+# NPM-PASS: regallocfast<filter=wwm;no-clear-vregs>
# NPM-PASS: regallocfast<filter=vgpr>
---
name: f
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