[llvm] [AMDGPU] Support block load/store for CSR (PR #130013)

[Carl Ritson via llvm-commits]

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@@ -5831,6 +5831,16 @@ const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,
                                    IsAllocatable);
 }
 
+const TargetRegisterClass *
+SIInstrInfo::getRegClassForBlockOp(const TargetRegisterInfo *TRI,
+                                   const MachineFunction &MF) const {
+  const MCInstrDesc &ScratchStoreBlockOp =
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perlfu wrote:

Can you expand on why this is retrieved from a specific instruction descriptor?

https://github.com/llvm/llvm-project/pull/130013