[llvm] [Mips] Fix clang crashes when compiling a variadic function while tar… (PR #130558)
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Mon Mar 10 00:40:35 PDT 2025
https://github.com/yingopq created https://github.com/llvm/llvm-project/pull/130558
…geting mips3
issue reason:
Because mips3 has the feature 'FeatureGP64Bit', when target mips3 process function `writeVarArgRegs`, the result of `getGPRSizeInBytes` is 8 and the result of 'GetVarArgRegs' is 'Mips::A0, Mips::A1, Mips::A2, Mips::A3'. This would generate `gpr64 = COPY $a1` which should be 'gpr64 = COPY $a1_64'.
Fix #98716.
>From 38ea768470c402dee4331f0286036e07ee68e508 Mon Sep 17 00:00:00 2001
From: Ying Huang <ying.huang at oss.cipunited.com>
Date: Sun, 9 Mar 2025 23:13:26 -0400
Subject: [PATCH] [Mips] Fix clang crashes when compiling a variadic function
while targeting mips3
issue reason:
Because mips3 has the feature 'FeatureGP64Bit', when target mips3 process
function `writeVarArgRegs`, the result of `getGPRSizeInBytes` is 8 and
the result of 'GetVarArgRegs' is 'Mips::A0, Mips::A1, Mips::A2, Mips::A3'.
This would generate `gpr64 = COPY $a1` which should be 'gpr64 = COPY $a1_64'.
Fix #98716.
---
.../Target/Mips/MCTargetDesc/MipsABIInfo.cpp | 10 ++--
.../Target/Mips/MCTargetDesc/MipsABIInfo.h | 2 +-
llvm/lib/Target/Mips/MipsCallLowering.cpp | 3 +-
llvm/lib/Target/Mips/MipsISelLowering.cpp | 3 +-
.../Mips/variable-function-arguments.ll | 53 +++++++++++++++++++
5 files changed, 64 insertions(+), 7 deletions(-)
create mode 100644 llvm/test/CodeGen/Mips/variable-function-arguments.ll
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
index 08cbba952ccc8..f2005f209e408 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
@@ -37,9 +37,13 @@ ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
llvm_unreachable("Unhandled ABI");
}
-ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const {
- if (IsO32())
- return ArrayRef(O32IntRegs);
+ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs(bool isGP64bit) const {
+ if (IsO32()) {
+ if (isGP64bit)
+ return ArrayRef(Mips64IntRegs);
+ else
+ return ArrayRef(O32IntRegs);
+ }
if (IsN32() || IsN64())
return ArrayRef(Mips64IntRegs);
llvm_unreachable("Unhandled ABI");
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
index 41f80771142de..d1755c4101720 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
@@ -46,7 +46,7 @@ class MipsABIInfo {
ArrayRef<MCPhysReg> GetByValArgRegs() const;
/// The registers to use for the variable argument list.
- ArrayRef<MCPhysReg> GetVarArgRegs() const;
+ ArrayRef<MCPhysReg> GetVarArgRegs(bool isGP64bit) const;
/// Obtain the size of the area allocated by the callee for arguments.
/// CallingConv::FastCall affects the value for O32.
diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp
index b856290211277..c0fc9fc66e3d8 100644
--- a/llvm/lib/Target/Mips/MipsCallLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp
@@ -406,7 +406,8 @@ bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
return false;
if (F.isVarArg()) {
- ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
+ ArrayRef<MCPhysReg> ArgRegs =
+ ABI.GetVarArgRegs(MF.getSubtarget<MipsSubtarget>().isGP64bit());
unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
int VaArgOffset;
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index e737c5aeb43c6..4d7330abecffb 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -3400,7 +3400,6 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SDValue StackPtr =
DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
getPointerTy(DAG.getDataLayout()));
-
std::deque<std::pair<unsigned, SDValue>> RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
@@ -4640,7 +4639,7 @@ void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
SDValue Chain, const SDLoc &DL,
SelectionDAG &DAG,
CCState &State) const {
- ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
+ ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(Subtarget.isGP64bit());
unsigned Idx = State.getFirstUnallocated(ArgRegs);
unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
diff --git a/llvm/test/CodeGen/Mips/variable-function-arguments.ll b/llvm/test/CodeGen/Mips/variable-function-arguments.ll
new file mode 100644
index 0000000000000..70db53aaae732
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/variable-function-arguments.ll
@@ -0,0 +1,53 @@
+; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips3 -target-abi o32 < %s | FileCheck %s -check-prefixes=MIPS3-O32
+; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips3 -target-abi n32 < %s | FileCheck %s -check-prefixes=MIPS3-N32
+; RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips3 -target-abi n64 < %s | FileCheck %s -check-prefixes=MIPS3-N64
+
+define void @func(ptr noundef %x, ...) nounwind {
+; MIPS3-O32-LABEL: func:
+; MIPS32-O32: # %bb.0: # %entry
+; MIPS32-O32-NEXT: addiu $sp, $sp, -48
+; MIPS32-O32-NEXT: sd $11, 56($sp)
+; MIPS32-O32-NEXT: sd $10, 48($sp)
+; MIPS32-O32-NEXT: sd $9, 40($sp)
+; MIPS32-O32-NEXT: sd $8, 32($sp)
+; MIPS32-O32-NEXT: sd $7, 24($sp)
+; MIPS32-O32-NEXT: sd $6, 16($sp)
+; MIPS32-O32-NEXT: sd $5, 8($sp)
+; MIPS32-O32-NEXT: sw $4, 4($sp)
+; MIPS32-O32-NEXT: jr $ra
+; MIPS32-O32-NEXT: addiu $sp, $sp, 48
+;
+; MIPS3-N32-LABEL: func:
+; MIPS32-N32: # %bb.0: # %entry
+; MIPS32-N32-NEXT: addiu $sp, $sp, -64
+; MIPS32-N32-NEXT: sd $11, 56($sp)
+; MIPS32-N32-NEXT: sd $10, 48($sp)
+; MIPS32-N32-NEXT: sd $9, 40($sp)
+; MIPS32-N32-NEXT: sd $8, 32($sp)
+; MIPS32-N32-NEXT: sd $7, 24($sp)
+; MIPS32-N32-NEXT: sd $6, 16($sp)
+; MIPS32-N32-NEXT: sd $5, 8($sp)
+; MIPS32-N32-NEXT: sw $4, 4($sp)
+; MIPS32-N32-NEXT: jr $ra
+; MIPS32-N32-NEXT: addiu $sp, $sp, 64
+;
+; MIPS3-N64-LABEL: func:
+; MIPS32-N64: # %bb.0: # %entry
+; MIPS32-N64-NEXT: addiu $sp, $sp, -64
+; MIPS32-N64-NEXT: sdl $4, 7($sp)
+; MIPS32-N64-NEXT: sd $11, 56($sp)
+; MIPS32-N64-NEXT: sd $10, 48($sp)
+; MIPS32-N64-NEXT: sd $9, 40($sp)
+; MIPS32-N64-NEXT: sd $8, 32($sp)
+; MIPS32-N64-NEXT: sd $7, 24($sp)
+; MIPS32-N64-NEXT: sd $6, 16($sp)
+; MIPS32-N64-NEXT: sd $5, 8($sp)
+; MIPS32-N64-NEXT: sw $4, 4($sp)
+; MIPS32-N64-NEXT: jr $ra
+; MIPS32-N64-NEXT: addiu $sp, $sp, 64
+
+entry:
+ %x.addr = alloca ptr, align 4
+ store ptr %x, ptr %x.addr, align 4
+ ret void
+}
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