[llvm] 228dbd2 - [RegAllocGreedy] Use MCRegister instead of Register for functions that return a physical register.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 22 21:41:56 PST 2025
Author: Craig Topper
Date: 2025-02-22T21:39:25-08:00
New Revision: 228dbd254a5addeaa638b23e2e7a63ba4efc763e
URL: https://github.com/llvm/llvm-project/commit/228dbd254a5addeaa638b23e2e7a63ba4efc763e
DIFF: https://github.com/llvm/llvm-project/commit/228dbd254a5addeaa638b23e2e7a63ba4efc763e.diff
LOG: [RegAllocGreedy] Use MCRegister instead of Register for functions that return a physical register.
The callers of these functions return the value as an MCRegister
so this removes some casts from Register to MCRegister.
Added:
Modified:
llvm/lib/CodeGen/RegAllocGreedy.cpp
llvm/lib/CodeGen/RegAllocGreedy.h
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index f1e734dd2f933..1ef7ef3436e12 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -1189,9 +1189,9 @@ unsigned RAGreedy::calculateRegionSplitCost(const LiveInterval &VirtReg,
return BestCand;
}
-Register RAGreedy::doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
- bool HasCompact,
- SmallVectorImpl<Register> &NewVRegs) {
+MCRegister RAGreedy::doRegionSplit(const LiveInterval &VirtReg,
+ unsigned BestCand, bool HasCompact,
+ SmallVectorImpl<Register> &NewVRegs) {
SmallVector<unsigned, 8> UsedCands;
// Prepare split editor.
LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
@@ -1226,7 +1226,7 @@ Register RAGreedy::doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
}
splitAroundRegion(LREdit, UsedCands);
- return Register();
+ return MCRegister();
}
// VirtReg has a physical Hint, this function tries to split VirtReg around
@@ -1293,9 +1293,9 @@ bool RAGreedy::trySplitAroundHintReg(MCPhysReg Hint,
/// tryBlockSplit - Split a global live range around every block with uses. This
/// creates a lot of local live ranges, that will be split by tryLocalSplit if
/// they don't allocate.
-Register RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
- AllocationOrder &Order,
- SmallVectorImpl<Register> &NewVRegs) {
+MCRegister RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
+ AllocationOrder &Order,
+ SmallVectorImpl<Register> &NewVRegs) {
assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
Register Reg = VirtReg.reg();
bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
@@ -1308,7 +1308,7 @@ Register RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
}
// No blocks were split.
if (LREdit.empty())
- return Register();
+ return MCRegister();
// We did split for some blocks.
SmallVector<unsigned, 8> IntvMap;
@@ -1327,7 +1327,7 @@ Register RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
if (VerifyEnabled)
MF->verify(this, "After splitting live range around basic blocks", &errs());
- return Register();
+ return MCRegister();
}
//===----------------------------------------------------------------------===//
@@ -1414,16 +1414,16 @@ static bool readsLaneSubset(const MachineRegisterInfo &MRI,
/// be moved to a larger register class.
///
/// This is similar to spilling to a larger register class.
-Register RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
- AllocationOrder &Order,
- SmallVectorImpl<Register> &NewVRegs) {
+MCRegister RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
+ AllocationOrder &Order,
+ SmallVectorImpl<Register> &NewVRegs) {
const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg());
// There is no point to this if there are no larger sub-classes.
bool SplitSubClass = true;
if (!RegClassInfo.isProperSubClass(CurRC)) {
if (!VirtReg.hasSubRanges())
- return Register();
+ return MCRegister();
SplitSubClass = false;
}
@@ -1434,7 +1434,7 @@ Register RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
ArrayRef<SlotIndex> Uses = SA->getUseSlots();
if (Uses.size() <= 1)
- return Register();
+ return MCRegister();
LLVM_DEBUG(dbgs() << "Split around " << Uses.size()
<< " individual instrs.\n");
@@ -1469,7 +1469,7 @@ Register RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
if (LREdit.empty()) {
LLVM_DEBUG(dbgs() << "All uses were copies.\n");
- return Register();
+ return MCRegister();
}
SmallVector<unsigned, 8> IntvMap;
@@ -1477,7 +1477,7 @@ Register RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
DebugVars->splitRegister(VirtReg.reg(), LREdit.regs(), *LIS);
// Assign all new registers to RS_Spill. This was the last chance.
ExtraInfo->setStage(LREdit.begin(), LREdit.end(), RS_Spill);
- return Register();
+ return MCRegister();
}
//===----------------------------------------------------------------------===//
@@ -1567,13 +1567,13 @@ void RAGreedy::calcGapWeights(MCRegister PhysReg,
/// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
/// basic block.
///
-Register RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
- AllocationOrder &Order,
- SmallVectorImpl<Register> &NewVRegs) {
+MCRegister RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
+ AllocationOrder &Order,
+ SmallVectorImpl<Register> &NewVRegs) {
// TODO: the function currently only handles a single UseBlock; it should be
// possible to generalize.
if (SA->getUseBlocks().size() != 1)
- return Register();
+ return MCRegister();
const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
@@ -1586,7 +1586,7 @@ Register RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
ArrayRef<SlotIndex> Uses = SA->getUseSlots();
if (Uses.size() <= 2)
- return Register();
+ return MCRegister();
const unsigned NumGaps = Uses.size()-1;
LLVM_DEBUG({
@@ -1754,7 +1754,7 @@ Register RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
// Didn't find any candidates?
if (BestBefore == NumGaps)
- return Register();
+ return MCRegister();
LLVM_DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore] << '-'
<< Uses[BestAfter] << ", " << BestDiff << ", "
@@ -1788,7 +1788,7 @@ Register RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
}
++NumLocalSplits;
- return Register();
+ return MCRegister();
}
//===----------------------------------------------------------------------===//
@@ -1798,19 +1798,20 @@ Register RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
/// trySplit - Try to split VirtReg or one of its interferences, making it
/// assignable.
/// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
-Register RAGreedy::trySplit(const LiveInterval &VirtReg, AllocationOrder &Order,
- SmallVectorImpl<Register> &NewVRegs,
- const SmallVirtRegSet &FixedRegisters) {
+MCRegister RAGreedy::trySplit(const LiveInterval &VirtReg,
+ AllocationOrder &Order,
+ SmallVectorImpl<Register> &NewVRegs,
+ const SmallVirtRegSet &FixedRegisters) {
// Ranges must be Split2 or less.
if (ExtraInfo->getStage(VirtReg) >= RS_Spill)
- return Register();
+ return MCRegister();
// Local intervals are handled separately.
if (LIS->intervalIsInOneMBB(VirtReg)) {
NamedRegionTimer T("local_split", "Local Splitting", TimerGroupName,
TimerGroupDescription, TimePassesIsEnabled);
SA->analyze(&VirtReg);
- Register PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
+ MCRegister PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
if (PhysReg || !NewVRegs.empty())
return PhysReg;
return tryInstructionSplit(VirtReg, Order, NewVRegs);
@@ -1954,12 +1955,10 @@ bool RAGreedy::mayRecolorAllInterferences(
/// \p Depth gives the current depth of the last chance recoloring.
/// \return a physical register that can be used for VirtReg or ~0u if none
/// exists.
-Register RAGreedy::tryLastChanceRecoloring(const LiveInterval &VirtReg,
- AllocationOrder &Order,
- SmallVectorImpl<Register> &NewVRegs,
- SmallVirtRegSet &FixedRegisters,
- RecoloringStack &RecolorStack,
- unsigned Depth) {
+MCRegister RAGreedy::tryLastChanceRecoloring(
+ const LiveInterval &VirtReg, AllocationOrder &Order,
+ SmallVectorImpl<Register> &NewVRegs, SmallVirtRegSet &FixedRegisters,
+ RecoloringStack &RecolorStack, unsigned Depth) {
if (!TRI->shouldUseLastChanceRecoloringForVirtReg(*MF, VirtReg))
return ~0u;
@@ -2058,7 +2057,7 @@ Register RAGreedy::tryLastChanceRecoloring(const LiveInterval &VirtReg,
LLVM_DEBUG(dbgs() << "tryRecoloringCandidates deleted a fixed register "
<< printReg(ThisVirtReg) << '\n');
FixedRegisters.erase(ThisVirtReg);
- return Register();
+ return MCRegister();
}
LLVM_DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
@@ -2485,7 +2484,7 @@ MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval &VirtReg,
if (Stage < RS_Spill && !VirtReg.empty()) {
// Try splitting VirtReg or interferences.
unsigned NewVRegSizeBefore = NewVRegs.size();
- Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters);
+ MCRegister PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters);
if (PhysReg || (NewVRegs.size() - NewVRegSizeBefore))
return PhysReg;
}
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.h b/llvm/lib/CodeGen/RegAllocGreedy.h
index 1698607984bcd..d89b93e296533 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.h
+++ b/llvm/lib/CodeGen/RegAllocGreedy.h
@@ -358,8 +358,9 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public MachineFunctionPass,
BlockFrequency &BestCost,
unsigned &NumCands, bool IgnoreCSR);
/// Perform region splitting.
- Register doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
- bool HasCompact, SmallVectorImpl<Register> &NewVRegs);
+ MCRegister doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
+ bool HasCompact,
+ SmallVectorImpl<Register> &NewVRegs);
/// Try to split VirtReg around physical Hint register.
bool trySplitAroundHintReg(MCPhysReg Hint, const LiveInterval &VirtReg,
SmallVectorImpl<Register> &NewVRegs,
@@ -371,18 +372,18 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public MachineFunctionPass,
uint8_t &CostPerUseLimit,
SmallVectorImpl<Register> &NewVRegs);
void initializeCSRCost();
- Register tryBlockSplit(const LiveInterval &, AllocationOrder &,
- SmallVectorImpl<Register> &);
- Register tryInstructionSplit(const LiveInterval &, AllocationOrder &,
- SmallVectorImpl<Register> &);
- Register tryLocalSplit(const LiveInterval &, AllocationOrder &,
- SmallVectorImpl<Register> &);
- Register trySplit(const LiveInterval &, AllocationOrder &,
- SmallVectorImpl<Register> &, const SmallVirtRegSet &);
- Register tryLastChanceRecoloring(const LiveInterval &, AllocationOrder &,
- SmallVectorImpl<Register> &,
- SmallVirtRegSet &, RecoloringStack &,
- unsigned);
+ MCRegister tryBlockSplit(const LiveInterval &, AllocationOrder &,
+ SmallVectorImpl<Register> &);
+ MCRegister tryInstructionSplit(const LiveInterval &, AllocationOrder &,
+ SmallVectorImpl<Register> &);
+ MCRegister tryLocalSplit(const LiveInterval &, AllocationOrder &,
+ SmallVectorImpl<Register> &);
+ MCRegister trySplit(const LiveInterval &, AllocationOrder &,
+ SmallVectorImpl<Register> &, const SmallVirtRegSet &);
+ MCRegister tryLastChanceRecoloring(const LiveInterval &, AllocationOrder &,
+ SmallVectorImpl<Register> &,
+ SmallVirtRegSet &, RecoloringStack &,
+ unsigned);
bool tryRecoloringCandidates(PQueue &, SmallVectorImpl<Register> &,
SmallVirtRegSet &, RecoloringStack &, unsigned);
void tryHintRecoloring(const LiveInterval &);
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