[llvm] 6fe780c - [RegAllocGreedy] Use Register() instead of 0 for invalid Register. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-02-22T16:20:19-08:00
New Revision: 6fe780ce63acf947826289e4a7e0ecbe91cbf4ed

URL: https://github.com/llvm/llvm-project/commit/6fe780ce63acf947826289e4a7e0ecbe91cbf4ed
DIFF: https://github.com/llvm/llvm-project/commit/6fe780ce63acf947826289e4a7e0ecbe91cbf4ed.diff

LOG: [RegAllocGreedy] Use Register() instead of 0 for invalid Register. NFC

Added: 
    

Modified: 
    llvm/lib/CodeGen/RegAllocGreedy.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index bd81d630f9d1f..a9481c70ec242 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -1423,7 +1423,7 @@ Register RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
   bool SplitSubClass = true;
   if (!RegClassInfo.isProperSubClass(CurRC)) {
     if (!VirtReg.hasSubRanges())
-      return 0;
+      return Register();
     SplitSubClass = false;
   }
 
@@ -1434,7 +1434,7 @@ Register RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
 
   ArrayRef<SlotIndex> Uses = SA->getUseSlots();
   if (Uses.size() <= 1)
-    return 0;
+    return Register();
 
   LLVM_DEBUG(dbgs() << "Split around " << Uses.size()
                     << " individual instrs.\n");
@@ -1586,7 +1586,7 @@ Register RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
 
   ArrayRef<SlotIndex> Uses = SA->getUseSlots();
   if (Uses.size() <= 2)
-    return 0;
+    return Register();
   const unsigned NumGaps = Uses.size()-1;
 
   LLVM_DEBUG({
@@ -2184,7 +2184,7 @@ MCRegister RAGreedy::selectOrSplit(const LiveInterval &VirtReg,
 /// range can have lower cost than using the CSR for the first time;
 /// Spilling a live range in the cold path can have lower cost than using
 /// the CSR for the first time. Returns the physical register if we decide
-/// to use the CSR; otherwise return 0.
+/// to use the CSR; otherwise return MCRegister().
 MCRegister RAGreedy::tryAssignCSRFirstTime(
     const LiveInterval &VirtReg, AllocationOrder &Order, MCRegister PhysReg,
     uint8_t &CostPerUseLimit, SmallVectorImpl<Register> &NewVRegs) {