[llvm] [RISCV] Remove unnecessary entries from RISCVVInversePseudosTable. NFC (PR #128376)

via llvm-commits llvm-commits at lists.llvm.org
Sat Feb 22 15:06:37 PST 2025


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

The inverse pseudos table contained entries that map back to the unmasked and masked pseudo, but the lookup only returns the first one.

Add a new class so we can control which instructions have an inverse in the table.

This reduces the size of the llvm-mca binary by ~32KB.

---
Full diff: https://github.com/llvm/llvm-project/pull/128376.diff


3 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+36-33) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td (+6-6) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td (+2-2) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 1795bf73d0a22..f7a45fe224620 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -557,6 +557,9 @@ class RISCVVPseudo {
   bit NeedBeInPseudoTable = 1;
 }
 
+// Class to filter for the RISCVVInversePseudosTable.
+class RISCVVPseudoInverse : RISCVVPseudo;
+
 // The actual table.
 def RISCVVPseudosTable : GenericTable {
   let FilterClass = "RISCVVPseudo";
@@ -569,7 +572,7 @@ def RISCVVPseudosTable : GenericTable {
 }
 
 def RISCVVInversePseudosTable : GenericTable {
-  let FilterClass = "RISCVVPseudo";
+  let FilterClass = "RISCVVPseudoInverse";
   let CppTypeName = "PseudoInfo";
   let Fields = [ "Pseudo", "BaseInstr", "VLMul", "SEW"];
   let PrimaryKey = [ "BaseInstr", "VLMul", "SEW"];
@@ -785,7 +788,7 @@ class VPseudoUSLoadNoMask<VReg RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sewop:$sew,
                   vec_policy:$policy), []>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
@@ -819,7 +822,7 @@ class VPseudoUSLoadFFNoMask<VReg RetClass,
       Pseudo<(outs RetClass:$rd, GPR:$vl),
              (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
                   sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
@@ -853,7 +856,7 @@ class VPseudoSLoadNoMask<VReg RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl,
                   sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
@@ -892,7 +895,7 @@ class VPseudoILoadNoMask<VReg RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
                   sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
@@ -933,7 +936,7 @@ class VPseudoUSStoreNoMask<VReg StClass,
                            DAGOperand sewop = sew> :
       Pseudo<(outs),
              (ins StClass:$rd, GPRMem:$rs1, AVL:$vl, sewop:$sew), []>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
@@ -961,7 +964,7 @@ class VPseudoSStoreNoMask<VReg StClass,
       Pseudo<(outs),
              (ins StClass:$rd, GPRMem:$rs1, GPR:$rs2,
                   AVL:$vl, sew:$sew), []>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVSE</*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
@@ -988,7 +991,7 @@ class VPseudoNullaryNoMask<VReg RegClass> :
       Pseudo<(outs RegClass:$rd),
              (ins RegClass:$passthru,
                   AVL:$vl, sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -1037,7 +1040,7 @@ class VPseudoUnaryNoMask<DAGOperand RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$passthru, OpClass:$rs2,
                   AVL:$vl, sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -1054,7 +1057,7 @@ class VPseudoUnaryNoMaskNoPolicy<DAGOperand RetClass,
                                  bits<2> TargetConstraintType = 1> :
       Pseudo<(outs RetClass:$rd),
              (ins OpClass:$rs2, AVL:$vl, sew_mask:$sew), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -1071,7 +1074,7 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm,
                   AVL:$vl, sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -1148,7 +1151,7 @@ class VPseudoUnaryMask_NoExcept<VReg RetClass,
 class VPseudoUnaryNoMaskGPROut :
       Pseudo<(outs GPR:$rd),
              (ins VR:$rs2, AVL:$vl, sew_mask:$sew), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -1173,7 +1176,7 @@ class VPseudoUnaryAnyMask<VReg RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$passthru, Op1Class:$rs2,
                   VR:$vm, AVL:$vl, sew:$sew), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -1190,7 +1193,7 @@ class VPseudoBinaryNoMask<VReg RetClass,
                           DAGOperand sewop = sew> :
       Pseudo<(outs RetClass:$rd),
              (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -1208,7 +1211,7 @@ class VPseudoBinaryNoMaskPolicy<VReg RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl,
                   sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -1228,7 +1231,7 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, vec_rm:$rm,
                   AVL:$vl, sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");
@@ -1319,7 +1322,7 @@ class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
       Pseudo<(outs),
              (ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
                   sew:$sew),[]>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
@@ -1487,7 +1490,7 @@ class VPseudoBinaryCarry<VReg RetClass,
                      VMV0:$carry, AVL:$vl, sew:$sew),
                 (ins Op1Class:$rs2, Op2Class:$rs1,
                      AVL:$vl, sew:$sew)), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -1506,7 +1509,7 @@ class VPseudoTiedBinaryCarryIn<VReg RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1,
                   VMV0:$carry, AVL:$vl, sew:$sew), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -1525,7 +1528,7 @@ class VPseudoTernaryNoMask<VReg RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
                   AVL:$vl, sew:$sew), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -1542,7 +1545,7 @@ class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
                   AVL:$vl, sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -1561,7 +1564,7 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
                   vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -1581,7 +1584,7 @@ class VPseudoUSSegLoadNoMask<VReg RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl,
                   sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
@@ -1616,7 +1619,7 @@ class VPseudoUSSegLoadFFNoMask<VReg RetClass,
       Pseudo<(outs RetClass:$rd, GPR:$vl),
              (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
                   sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
@@ -1651,7 +1654,7 @@ class VPseudoSSegLoadNoMask<VReg RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$passthru, GPRMem:$rs1, GPR:$offset, AVL:$vl,
                  sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
   let mayLoad = 1;
   let mayStore = 0;
@@ -1690,7 +1693,7 @@ class VPseudoISegLoadNoMask<VReg RetClass,
       Pseudo<(outs RetClass:$rd),
              (ins RetClass:$passthru, GPRMem:$rs1, IdxClass:$offset, AVL:$vl,
                   sew:$sew, vec_policy:$policy), []>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
   let mayLoad = 1;
   let mayStore = 0;
@@ -1732,7 +1735,7 @@ class VPseudoUSSegStoreNoMask<VReg ValClass,
                               bits<4> NF> :
       Pseudo<(outs),
              (ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
@@ -1762,7 +1765,7 @@ class VPseudoSSegStoreNoMask<VReg ValClass,
       Pseudo<(outs),
              (ins ValClass:$rd, GPRMem:$rs1, GPR:$offset,
                   AVL:$vl, sew:$sew), []>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
   let mayLoad = 0;
   let mayStore = 1;
@@ -1795,7 +1798,7 @@ class VPseudoISegStoreNoMask<VReg ValClass,
       Pseudo<(outs),
              (ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
                   AVL:$vl, sew:$sew), []>,
-      RISCVVPseudo,
+      RISCVVPseudoInverse,
       RISCVVSXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
   let mayLoad = 0;
   let mayStore = 1;
@@ -6680,14 +6683,14 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
   def PseudoVMV_X_S:
     Pseudo<(outs GPR:$rd), (ins VR:$rs2, sew:$sew), []>,
     Sched<[WriteVMovXS, ReadVMovXS]>,
-    RISCVVPseudo;
+    RISCVVPseudoInverse;
   let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, isReMaterializable = 1,
       Constraints = "$rd = $rs1" in
   def PseudoVMV_S_X: Pseudo<(outs VR:$rd),
                             (ins VR:$rs1, GPR:$rs2, AVL:$vl, sew:$sew),
                             []>,
     Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>,
-    RISCVVPseudo;
+    RISCVVPseudoInverse;
 }
 } // Predicates = [HasVInstructions]
 
@@ -6703,7 +6706,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
       Pseudo<(outs f.fprclass:$rd),
              (ins VR:$rs2, sew:$sew), []>,
       Sched<[WriteVMovFS, ReadVMovFS]>,
-      RISCVVPseudo;
+      RISCVVPseudoInverse;
     let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, isReMaterializable = 1,
         Constraints = "$rd = $rs1" in
     def "PseudoVFMV_S_" # f.FX :
@@ -6711,7 +6714,7 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
              (ins VR:$rs1, f.fprclass:$rs2, AVL:$vl, sew:$sew),
              []>,
       Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>,
-      RISCVVPseudo;
+      RISCVVPseudoInverse;
   }
 }
 } // Predicates = [HasVInstructionsAnyF]
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index 0654f1ac19a82..103fa475f864a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -232,7 +232,7 @@ class VPseudoVC_X<Operand OpClass, DAGOperand RS1Class> :
       Pseudo<(outs),
              (ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1,
                   AVL:$vl, sew:$sew), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let HasVLOp = 1;
@@ -244,7 +244,7 @@ class VPseudoVC_XV<Operand OpClass, VReg RS2Class, DAGOperand RS1Class> :
       Pseudo<(outs),
              (ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1,
                   AVL:$vl, sew:$sew), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let HasVLOp = 1;
@@ -257,7 +257,7 @@ class VPseudoVC_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
       Pseudo<(outs),
              (ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1,
                   AVL:$vl, sew:$sew), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let HasVLOp = 1;
@@ -269,7 +269,7 @@ class VPseudoVC_V_X<Operand OpClass, VReg RDClass, DAGOperand RS1Class> :
       Pseudo<(outs RDClass:$rd),
              (ins OpClass:$op1, payload5:$rs2, RS1Class:$r1,
                   AVL:$vl, sew:$sew), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let HasVLOp = 1;
@@ -282,7 +282,7 @@ class VPseudoVC_V_XV<Operand OpClass, VReg RDClass, VReg RS2Class,
       Pseudo<(outs RDClass:$rd),
              (ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1,
                   AVL:$vl, sew:$sew), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let HasVLOp = 1;
@@ -295,7 +295,7 @@ class VPseudoVC_V_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
       Pseudo<(outs RDClass:$rd),
              (ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1,
                   AVL:$vl, sew:$sew), []>,
-      RISCVVPseudo {
+      RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let HasVLOp = 1;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 470555769d493..14f8c5300d1ff 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -232,7 +232,7 @@ class ZvkMxSet<string vd_lmul> {
 class VPseudoBinaryNoMask_Zvk<DAGOperand RetClass, VReg OpClass> :
       Pseudo<(outs RetClass:$rd_wb),
         (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
-        RISCVVPseudo {
+        RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
@@ -249,7 +249,7 @@ class VPseudoTernaryNoMask_Zvk<VReg RetClass,
         Pseudo<(outs RetClass:$rd_wb),
                (ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1,
                     AVL:$vl, sew:$sew, vec_policy:$policy), []>,
-        RISCVVPseudo {
+        RISCVVPseudoInverse {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;

``````````

</details>


https://github.com/llvm/llvm-project/pull/128376


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