[llvm] 75bb25b - [Xtensa] Use asMCReg after #128095
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 22 11:48:06 PST 2025
Author: Fangrui Song
Date: 2025-02-22T11:48:01-08:00
New Revision: 75bb25b682527f7ebb4818502625cee8b36d2d46
URL: https://github.com/llvm/llvm-project/commit/75bb25b682527f7ebb4818502625cee8b36d2d46
DIFF: https://github.com/llvm/llvm-project/commit/75bb25b682527f7ebb4818502625cee8b36d2d46.diff
LOG: [Xtensa] Use asMCReg after #128095
Added:
Modified:
llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
index 3fc0c47c528d3..7ff6ff81bc28e 100644
--- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
@@ -83,10 +83,11 @@ void XtensaFrameLowering::emitPrologue(MachineFunction &MF,
if (MBBI->getOpcode() == TargetOpcode::COPY && Info.isSpilledToReg()) {
Register DstReg = MBBI->getOperand(0).getReg();
Register Reg = MBBI->getOperand(1).getReg();
- IsStoreInst = (Info.getDstReg() == DstReg) && (Info.getReg() == Reg);
+ IsStoreInst =
+ Info.getDstReg() == DstReg && Info.getReg() == Reg.asMCReg();
} else {
Register Reg = TII.isStoreToStackSlot(*MBBI, StoreFI);
- IsStoreInst = (Reg == Info.getReg()) && (StoreFI == FI);
+ IsStoreInst = Reg.asMCReg() == Info.getReg() && StoreFI == FI;
}
assert(IsStoreInst &&
"Unexpected callee-saved register store instruction");
@@ -168,10 +169,11 @@ void XtensaFrameLowering::emitEpilogue(MachineFunction &MF,
if (I->getOpcode() == TargetOpcode::COPY && Info.isSpilledToReg()) {
Register Reg = I->getOperand(0).getReg();
Register DstReg = I->getOperand(1).getReg();
- IsRestoreInst = (Info.getDstReg() == DstReg) && (Info.getReg() == Reg);
+ IsRestoreInst =
+ Info.getDstReg() == DstReg && Info.getReg() == Reg.asMCReg();
} else {
Register Reg = TII.isLoadFromStackSlot(*I, LoadFI);
- IsRestoreInst = (Info.getReg() == Reg) && (LoadFI == FI);
+ IsRestoreInst = Info.getReg() == Reg.asMCReg() && LoadFI == FI;
}
assert(IsRestoreInst &&
"Unexpected callee-saved register restore instruction");
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