[llvm] [RISCV][Outliner] Use MCRegister. NFC (PR #128291)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Sudharsan Veeravalli (svs-quic)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/128291.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+2-1) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+3-3) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 58eb48ed613df..2e5b03c2eba5a 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -200,7 +200,8 @@ static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
   return Desc.getNumOperands() - Offset;
 }
 
-static inline unsigned getTailExpandUseRegNo(const FeatureBitset &FeatureBits) {
+static inline MCRegister
+getTailExpandUseRegNo(const FeatureBitset &FeatureBits) {
   // For Zicfilp, PseudoTAIL should be expanded to a software guarded branch.
   // It means to use t2(x7) as rs1 of JALR to expand PseudoTAIL.
   return FeatureBits[RISCV::FeatureStdExtZicfilp] ? RISCV::X7 : RISCV::X6;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 98f620572301e..f50789f5963b0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2984,13 +2984,13 @@ static bool isCandidatePatchable(const MachineBasicBlock &MBB) {
 }
 
 static bool isMIReadsReg(const MachineInstr &MI, const TargetRegisterInfo *TRI,
-                         unsigned RegNo) {
+                         MCRegister RegNo) {
   return MI.readsRegister(RegNo, TRI) ||
          MI.getDesc().hasImplicitUseOfPhysReg(RegNo);
 }
 
 static bool isMIModifiesReg(const MachineInstr &MI,
-                            const TargetRegisterInfo *TRI, unsigned RegNo) {
+                            const TargetRegisterInfo *TRI, MCRegister RegNo) {
   return MI.modifiesRegister(RegNo, TRI) ||
          MI.getDesc().hasImplicitDefOfPhysReg(RegNo);
 }
@@ -3005,7 +3005,7 @@ static bool cannotInsertTailCall(const MachineBasicBlock &MBB) {
   // that can be used for expanding PseudoTAIL instruction,
   // then we cannot insert tail call.
   const TargetSubtargetInfo &STI = MBB.getParent()->getSubtarget();
-  unsigned TailExpandUseRegNo =
+  MCRegister TailExpandUseRegNo =
       RISCVII::getTailExpandUseRegNo(STI.getFeatureBits());
   for (const MachineInstr &MI : MBB) {
     if (isMIReadsReg(MI, STI.getRegisterInfo(), TailExpandUseRegNo))

``````````

</details>


https://github.com/llvm/llvm-project/pull/128291