[llvm] PeepholeOpt: Allow introducing subregister uses on reg_sequence (PR #127052)

LLVM Continuous Integration via llvm-commits llvm-commits at lists.llvm.org
Fri Feb 21 19:47:14 PST 2025


llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `llvm-clang-x86_64-expensive-checks-debian` running on `gribozavr4` while building `llvm` at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/16/builds/14186

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll' FAILED ********************
Exit Code: 2

Command Output (stderr):
--
RUN: at line 2: /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc < /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll --mattr=+mve.fp,+fp64 -o - | /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/FileCheck /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll
+ /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc --mattr=+mve.fp,+fp64 -o -
+ /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/FileCheck /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll

# After Peephole Optimizations
# Machine code for function mul_divequal: IsSSA, TracksLiveness
Frame Objects:
  fi#-2: size=16, align=8, fixed, at location [SP+16]
  fi#-1: size=16, align=8, fixed, at location [SP]
Function Live Ins: $r0 in %0, $r1 in %1, $r2 in %2, $r3 in %3

bb.0.entry:
  liveins: $r0, $r1, $r2, $r3
  %3:gpr = COPY $r3
  %2:gpr = COPY $r2
  %1:gpr = COPY $r1
  %0:gpr = COPY $r0
  %4:rgpr = t2ADDri %fixed-stack.0, 0, 14, $noreg, $noreg
  %5:dpr = VMOVDRR %2:gpr, %3:gpr, 14, $noreg
  %6:dpr = VMOVDRR %0:gpr, %1:gpr, 14, $noreg
  %7:rgpr = t2ADDri %fixed-stack.1, 0, 14, $noreg, $noreg
  %8:mqpr = MVE_VLDRWU32 killed %7:rgpr, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.1, align 8)
  %9:spr = COPY %8.ssub_2:mqpr
  %10:spr = COPY %8.ssub_0:mqpr
  %14:spr = IMPLICIT_DEF
  %16:spr = IMPLICIT_DEF
  %13:mqpr = REG_SEQUENCE %8.ssub_0:mqpr, %subreg.ssub_0, %9:spr, %subreg.ssub_1, %14:spr, %subreg.ssub_2, %16:spr, %subreg.ssub_3
  %18:spr = COPY %8.ssub_3:mqpr
  %19:spr = COPY %8.ssub_1:mqpr
  %23:spr = IMPLICIT_DEF
  %25:spr = IMPLICIT_DEF
  %22:mqpr = REG_SEQUENCE %19:spr, %subreg.ssub_0, %18:spr, %subreg.ssub_1, %23:spr, %subreg.ssub_2, %25:spr, %subreg.ssub_3
  %27:mqpr = MVE_VLDRWU32 killed %4:rgpr, 0, 0, $noreg, $noreg :: (load (s128) from %fixed-stack.0, align 8)
  %28:spr = COPY %27.ssub_3:mqpr
  %30:mqpr = REG_SEQUENCE killed %6:dpr, %subreg.dsub_0, %5:dpr, %subreg.dsub_1
  %31:spr = COPY %30.ssub_3:mqpr
  %32:spr = COPY %30.ssub_1:mqpr
  %36:spr = IMPLICIT_DEF
  %38:spr = IMPLICIT_DEF
  %35:mqpr = REG_SEQUENCE %32:spr, %subreg.ssub_0, %5.ssub_1:dpr, %subreg.ssub_1, %36:spr, %subreg.ssub_2, %38:spr, %subreg.ssub_3
  %40:spr = COPY %30.ssub_2:mqpr
  %41:spr = COPY %30.ssub_0:mqpr
  %45:spr = IMPLICIT_DEF
  %47:spr = IMPLICIT_DEF
  %44:mqpr = REG_SEQUENCE %30.ssub_0:mqpr, %subreg.ssub_0, %40:spr, %subreg.ssub_1, %45:spr, %subreg.ssub_2, %47:spr, %subreg.ssub_3
...

```

</details>

https://github.com/llvm/llvm-project/pull/127052


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