[clang] [llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)

[Min-Yih Hsu via llvm-commits]

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@@ -582,4 +586,15 @@ unsigned RISCVMCCodeEmitter::getRegReg(const MCInst &MI, unsigned OpNo,
   return Op | Op1 << 5;
 }
 
+unsigned RISCVMCCodeEmitter::getRVPGPRPair(const MCInst &MI, unsigned OpNo,
+                                           SmallVectorImpl<MCFixup> &Fixups,
+                                           const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+  assert(MO.isReg() && "Expected a register.");
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mshockwave wrote:

MCOperand::getReg already asserts if it's not register, so I think you can remove this line.

https://github.com/llvm/llvm-project/pull/123271