[llvm] [RISCV] Simplify the debug messages in the disassembler. (PR #128102)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 21 09:46:48 PST 2025
================
@@ -622,106 +622,96 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
!STI.hasFeature(RISCV::Feature64Bit),
DecoderTableRV32Zdinx32,
- "RV32Zdinx table (Double in Integer and rv32)");
+ "RV32Zdinx (Double in Integer and rv32)");
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZacas) &&
!STI.hasFeature(RISCV::Feature64Bit),
DecoderTableRV32Zacas32,
- "RV32Zacas table (Compare-And-Swap and rv32)");
+ "RV32Zacas (Compare-And-Swap and rv32)");
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
- "RVZfinx table (Float in Integer)");
+ "RVZfinx (Float in Integer)");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
- DecoderTableXVentana32, "Ventana custom opcode table");
+ DecoderTableXVentana32, "XVentanaCondOps");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
- "XTHeadBa custom opcode table");
+ "XTHeadBa");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32,
- "XTHeadBb custom opcode table");
+ "XTHeadBb");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32,
- "XTHeadBs custom opcode table");
+ "XTHeadBs");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCondMov,
- DecoderTableXTHeadCondMov32,
- "XTHeadCondMov custom opcode table");
+ DecoderTableXTHeadCondMov32, "XTHeadCondMov");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32,
- "XTHeadCmo custom opcode table");
+ "XTHeadCmo");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadFMemIdx,
- DecoderTableXTHeadFMemIdx32,
- "XTHeadFMemIdx custom opcode table");
+ DecoderTableXTHeadFMemIdx32, "XTHeadFMemIdx");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32,
- "XTHeadMac custom opcode table");
+ "XTHeadMac");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemIdx,
- DecoderTableXTHeadMemIdx32,
- "XTHeadMemIdx custom opcode table");
+ DecoderTableXTHeadMemIdx32, "XTHeadMemIdx");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair,
- DecoderTableXTHeadMemPair32,
- "XTHeadMemPair custom opcode table");
+ DecoderTableXTHeadMemPair32, "XTHeadMemPair");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync,
- DecoderTableXTHeadSync32,
- "XTHeadSync custom opcode table");
+ DecoderTableXTHeadSync32, "XTHeadSync");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot,
- DecoderTableXTHeadVdot32,
- "XTHeadVdot custom opcode table");
+ DecoderTableXTHeadVdot32, "XTHeadVdot");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
- "SiFive VCIX custom opcode table");
+ "SiFive VCIX");
TRY_TO_DECODE_FEATURE(
RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32,
- "SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table");
+ "SiFive Matrix Multiplication (2x8 and 8x2) Instruction");
TRY_TO_DECODE_FEATURE(
RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32,
- "SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table");
- TRY_TO_DECODE_FEATURE(
- RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
- "SiFive Matrix Multiplication Instruction opcode table");
- TRY_TO_DECODE_FEATURE(
- RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
- "SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
+ "SiFive Matrix Multiplication (4x8 and 8x4) Instruction");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvfwmaccqqq,
+ DecoderTableXSfvfwmaccqqq32,
+ "SiFive Matrix Multiplication Instruction");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvfnrclipxfqf,
+ DecoderTableXSfvfnrclipxfqf32,
+ "SiFive FP32-to-int8 Ranged Clip Instructions");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone,
DecoderTableXSiFivecdiscarddlone32,
- "SiFive sf.cdiscard.d.l1 custom opcode table");
+ "SiFive sf.cdiscard.d.l1");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone,
DecoderTableXSiFivecflushdlone32,
- "SiFive sf.cflush.d.l1 custom opcode table");
+ "SiFive sf.cflush.d.l1");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
- "SiFive sf.cease custom opcode table");
+ "SiFive sf.cease");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXMIPSLSP, DecoderTableXmipslsp32,
- "MIPS mips.lsp custom opcode table");
+ "MIPS mips.lsp");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXMIPSCMove,
- DecoderTableXmipscmove32,
- "MIPS mips.ccmov custom opcode table");
+ DecoderTableXmipscmove32, "MIPS mips.ccmov");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
- DecoderTableXCVbitmanip32,
- "CORE-V Bit Manipulation custom opcode table");
+ DecoderTableXCVbitmanip32, "CORE-V Bit Manipulation");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
- "CORE-V Event load custom opcode table");
+ "CORE-V Event load");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
- "CORE-V MAC custom opcode table");
+ "CORE-V MAC");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
- "CORE-V MEM custom opcode table");
+ "CORE-V MEM");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
- "CORE-V ALU custom opcode table");
+ "CORE-V ALU");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
- "CORE-V SIMD extensions custom opcode table");
+ "CORE-V SIMD extensions");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
- "CORE-V Immediate Branching custom opcode table");
+ "CORE-V Immediate Branching");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicsr, DecoderTableXqcicsr32,
- "Qualcomm uC CSR custom opcode table");
+ "Qualcomm uC CSR");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32,
- "Qualcomm uC Scaled Load Store custom opcode table");
+ "Qualcomm uC Scaled Load Store");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcia, DecoderTableXqcia32,
- "Qualcomm uC Arithmetic custom opcode table");
+ "Qualcomm uC Arithmetic");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcics, DecoderTableXqcics32,
- "Qualcomm uC Conditional Select custom opcode table");
+ "Qualcomm uC Conditional Select");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcilsm, DecoderTableXqcilsm32,
- "Qualcomm uC Load Store Multiple custom opcode table");
- TRY_TO_DECODE_FEATURE(
- RISCV::FeatureVendorXqciac, DecoderTableXqciac32,
- "Qualcomm uC Load-Store Address Calculation custom opcode table");
- TRY_TO_DECODE_FEATURE(
- RISCV::FeatureVendorXqcicli, DecoderTableXqcicli32,
- "Qualcomm uC Conditional Load Immediate custom opcode table");
+ "Qualcomm uC Load Store Multiple");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciac, DecoderTableXqciac32,
+ "Qualcomm uC Load-Store Address Calculation");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicli, DecoderTableXqcicli32,
+ "Qualcomm uC Conditional Load Immediate");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicm, DecoderTableXqcicm32,
- "Qualcomm uC Conditional Move custom opcode table");
+ "Qualcomm uC Conditional Move");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint32,
- "Qualcomm uC Interrupts custom opcode table");
- TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
+ "Qualcomm uC Interrupts");
+ TRY_TO_DECODE(true, DecoderTable32, "RISCV32");
----------------
topperc wrote:
For the DinX/FinX/Acas cases there should be predicate checks in those tables and in the base table that make them mutex. So the order shouldn't matter.
https://github.com/llvm/llvm-project/pull/128102
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