[llvm] fb25216 - [AMDGPU] Enhance verification of amdgcn.cs.chain intrinsic (#128162)

[via llvm-commits]

Author: Robert Imschweiler
Date: 2025-02-22T00:24:18+07:00
New Revision: fb25216209c4d6f686bcb9f7fbc3ac0a8f5a61fa

URL: https://github.com/llvm/llvm-project/commit/fb25216209c4d6f686bcb9f7fbc3ac0a8f5a61fa
DIFF: https://github.com/llvm/llvm-project/commit/fb25216209c4d6f686bcb9f7fbc3ac0a8f5a61fa.diff

LOG: [AMDGPU] Enhance verification of amdgcn.cs.chain intrinsic (#128162)

Make sure that this intrinsic is being followed by unreachable.

This LLVM defect was identified via the AMD Fuzzing project.

Thanks to @rovka for helping me solve this issue!

Added: 
    

Modified: 
    llvm/lib/IR/Verifier.cpp
    llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 8432779c107de..58fd575e6e7e8 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -6367,6 +6367,8 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) {
           "SGPR arguments must have the `inreg` attribute", &Call);
     Check(!Call.paramHasAttr(3, Attribute::InReg),
           "VGPR arguments must not have the `inreg` attribute", &Call);
+    Check(isa_and_present<UnreachableInst>(Call.getNextNode()),
+          "llvm.amdgcn.cs.chain must be followed by unreachable", &Call);
     break;
   }
   case Intrinsic::amdgcn_set_inactive_chain_arg: {

diff  --git a/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll b/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
index b9e6e1eb45905..e6fba2c50dad4 100644
--- a/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
+++ b/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
@@ -32,6 +32,13 @@ define amdgpu_cs_chain void @bad_exec(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr,
   unreachable
 }
 
+define amdgpu_cs_chain void @not_unreachable(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {
+  ; CHECK: llvm.amdgcn.cs.chain must be followed by unreachable
+  ; CHECK-NEXT: @llvm.amdgcn.cs.chain
+  call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)
+  ret void
+}
+
 define void @bad_caller_default_cc(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {
   ; CHECK: Intrinsic can only be used from functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions
   ; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg