[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Ricardo Jesus via llvm-commits]

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@@ -23845,6 +23873,30 @@ static SDValue combineI8TruncStore(StoreSDNode *ST, SelectionDAG &DAG,
   return Chain;
 }
 
+// Replace scalable stores with fixed stores when vscale_range(1, 1).
+static SDValue combineVScale1Store(StoreSDNode *ST, SelectionDAG &DAG,
+                                   const AArch64Subtarget *Subtarget) {
+  SDValue Value = ST->getValue();
+  EVT ValueVT = Value.getValueType();
+  if (ST->isVolatile() || !Subtarget->isLittleEndian() ||
+      !Subtarget->isNeonAvailable() || !ValueVT.isScalableVector() ||
+      Subtarget->getMaxSVEVectorSizeInBits() != AArch64::SVEBitsPerBlock)
+    return SDValue();
+
+  // Skip unpacked types given their different layouts between Neon and SVE.
+  if (ValueVT.getSizeInBits().getKnownMinValue() != AArch64::SVEBitsPerBlock)
+    return SDValue();
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rj-jesus wrote:

Thanks, done.

https://github.com/llvm/llvm-project/pull/127500