[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Ricardo Jesus via llvm-commits]

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@@ -23550,6 +23550,31 @@ static SDValue combineV3I8LoadExt(LoadSDNode *LD, SelectionDAG &DAG) {
   return DAG.getMergeValues({Extract, TokenFactor}, DL);
 }
 
+// Replace scalable loads with fixed loads when vscale_range(1, 1).
+// This enables further optimisations such as LDP folds.
+static SDValue combineVScale1Load(LoadSDNode *LD, SelectionDAG &DAG,
+                                  const AArch64Subtarget *Subtarget) {
+  EVT MemVT = LD->getMemoryVT();
+  if (!Subtarget->isNeonAvailable() || !MemVT.isScalableVector() ||
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rj-jesus wrote:

Thanks, I think you're right, I've changed `isNeonAvailable` to `hasNEON`.

It should indeed be restricted to little-endian only, but I believe this is already enforced in `performLOADCombine` (see https://github.com/llvm/llvm-project/blob/90802ec069a88ebce7de370658093ed919480fb8/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L23609). Would you rather have a check here in any case?

https://github.com/llvm/llvm-project/pull/127500