[llvm] [AMDGPU] Enhance verification of amdgcn.cs.chain intrinsic (PR #128162)

[Robert Imschweiler via llvm-commits]

https://github.com/ro-i updated https://github.com/llvm/llvm-project/pull/128162

>From cccb6ad33d294a4001119f8e317c73d148967435 Mon Sep 17 00:00:00 2001
From: Robert Imschweiler <robert.imschweiler at amd.com>
Date: Fri, 21 Feb 2025 04:52:23 -0600
Subject: [PATCH 1/2] [AMDGPU] Enhance verification of amdgcn.cs.chain
 intrinsic

Make sure that this intrinsic is being followed by unreachable.

This LLVM defect was identified via the AMD Fuzzing project.
---
 llvm/lib/IR/Verifier.cpp                               | 2 ++
 llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll | 9 ++++++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 8432779c107de..0ba3c345795b7 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -6367,6 +6367,8 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) {
           "SGPR arguments must have the `inreg` attribute", &Call);
     Check(!Call.paramHasAttr(3, Attribute::InReg),
           "VGPR arguments must not have the `inreg` attribute", &Call);
+    Check(dyn_cast_or_null<UnreachableInst>(Call.getNextNode()),
+          "amdgcn_cs_chain must precede unreachable", &Call);
     break;
   }
   case Intrinsic::amdgcn_set_inactive_chain_arg: {
diff --git a/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll b/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
index b9e6e1eb45905..cd66e6fdf4ceb 100644
--- a/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
+++ b/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
@@ -32,6 +32,13 @@ define amdgpu_cs_chain void @bad_exec(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr,
   unreachable
 }
 
+define amdgpu_cs_chain void @not_unreachable(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {
+  ; CHECK: amdgcn_cs_chain must precede unreachable
+  ; CHECK-NEXT: @llvm.amdgcn.cs.chain
+  call void(ptr, i32, <4 x i32>, { ptr, <3 x i32> }, i32, ...) @llvm.amdgcn.cs.chain(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr, i32 0)
+  ret void
+}
+
 define void @bad_caller_default_cc(ptr %fn, i32 %exec, <4 x i32> inreg %sgpr, { ptr, <3 x i32> } %vgpr) {
   ; CHECK: Intrinsic can only be used from functions with the amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions
   ; CHECK-NEXT: @llvm.amdgcn.set.inactive.chain.arg
@@ -117,4 +124,4 @@ define amdgpu_cs_chain void @set_inactive_chain_arg_inreg(ptr addrspace(1) %out,
   %tmp = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 %active, i32 inreg %inactive) #0
   store i32 %tmp, ptr addrspace(1) %out
   ret void
-}
+}
\ No newline at end of file

>From 921a1baf2fc8fd79f33f37aba88ac3e6d06f1b76 Mon Sep 17 00:00:00 2001
From: Robert Imschweiler <robert.imschweiler at amd.com>
Date: Fri, 21 Feb 2025 07:17:59 -0600
Subject: [PATCH 2/2] implement feedback

---
 llvm/lib/IR/Verifier.cpp                               | 2 +-
 llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 0ba3c345795b7..809cfe81ee896 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -6367,7 +6367,7 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) {
           "SGPR arguments must have the `inreg` attribute", &Call);
     Check(!Call.paramHasAttr(3, Attribute::InReg),
           "VGPR arguments must not have the `inreg` attribute", &Call);
-    Check(dyn_cast_or_null<UnreachableInst>(Call.getNextNode()),
+    Check(isa_and_present<UnreachableInst>(Call.getNextNode()),
           "amdgcn_cs_chain must precede unreachable", &Call);
     break;
   }
diff --git a/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll b/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
index cd66e6fdf4ceb..aea08529a395c 100644
--- a/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
+++ b/llvm/test/Verifier/AMDGPU/intrinsic-amdgpu-cs-chain.ll
@@ -124,4 +124,4 @@ define amdgpu_cs_chain void @set_inactive_chain_arg_inreg(ptr addrspace(1) %out,
   %tmp = call i32 @llvm.amdgcn.set.inactive.chain.arg(i32 %active, i32 inreg %inactive) #0
   store i32 %tmp, ptr addrspace(1) %out
   ret void
-}
\ No newline at end of file
+}