[llvm] db98767 - [AArch64][GlobalISel] Add some gisel test coverage for existing select tests. NFC

David Green via llvm-commits llvm-commits at lists.llvm.org
Fri Feb 21 01:15:46 PST 2025


Author: David Green
Date: 2025-02-21T09:15:41Z
New Revision: db9876760f227cbe30fb882797c9b5e5e00523f2

URL: https://github.com/llvm/llvm-project/commit/db9876760f227cbe30fb882797c9b5e5e00523f2
DIFF: https://github.com/llvm/llvm-project/commit/db9876760f227cbe30fb882797c9b5e5e00523f2.diff

LOG: [AArch64][GlobalISel] Add some gisel test coverage for existing select tests. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/select-constant-xor.ll
    llvm/test/CodeGen/AArch64/select-to-and-zext.ll
    llvm/test/CodeGen/AArch64/select-with-and-or.ll
    llvm/test/CodeGen/AArch64/select_cc.ll
    llvm/test/CodeGen/AArch64/select_const.ll
    llvm/test/CodeGen/AArch64/select_fmf.ll
    llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/select-constant-xor.ll b/llvm/test/CodeGen/AArch64/select-constant-xor.ll
index 3adf48e84b44c..6803411f66896 100644
--- a/llvm/test/CodeGen/AArch64/select-constant-xor.ll
+++ b/llvm/test/CodeGen/AArch64/select-constant-xor.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-elf %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-elf %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-none-elf -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 define i32 @xori64i32(i64 %a) {
 ; CHECK-LABEL: xori64i32:
@@ -14,34 +15,59 @@ define i32 @xori64i32(i64 %a) {
 }
 
 define i64 @selecti64i64(i64 %a) {
-; CHECK-LABEL: selecti64i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    asr x8, x0, #63
-; CHECK-NEXT:    eor x0, x8, #0x7fffffff
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: selecti64i64:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    asr x8, x0, #63
+; CHECK-SD-NEXT:    eor x0, x8, #0x7fffffff
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: selecti64i64:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov x8, #-2147483648 // =0xffffffff80000000
+; CHECK-GI-NEXT:    mov w9, #2147483647 // =0x7fffffff
+; CHECK-GI-NEXT:    cmp x0, #0
+; CHECK-GI-NEXT:    csel x0, x9, x8, ge
+; CHECK-GI-NEXT:    ret
   %c = icmp sgt i64 %a, -1
   %s = select i1 %c, i64 2147483647, i64 -2147483648
   ret i64 %s
 }
 
 define i32 @selecti64i32(i64 %a) {
-; CHECK-LABEL: selecti64i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    asr x8, x0, #63
-; CHECK-NEXT:    eor w0, w8, #0x7fffffff
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: selecti64i32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    asr x8, x0, #63
+; CHECK-SD-NEXT:    eor w0, w8, #0x7fffffff
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: selecti64i32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmp x0, #0
+; CHECK-GI-NEXT:    mov w9, #-2147483648 // =0x80000000
+; CHECK-GI-NEXT:    cset w8, ge
+; CHECK-GI-NEXT:    sbfx w8, w8, #0, #1
+; CHECK-GI-NEXT:    add w0, w8, w9
+; CHECK-GI-NEXT:    ret
   %c = icmp sgt i64 %a, -1
   %s = select i1 %c, i32 2147483647, i32 -2147483648
   ret i32 %s
 }
 
 define i64 @selecti32i64(i32 %a) {
-; CHECK-LABEL: selecti32i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT:    sbfx x8, x0, #31, #1
-; CHECK-NEXT:    eor x0, x8, #0x7fffffff
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: selecti32i64:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-SD-NEXT:    sbfx x8, x0, #31, #1
+; CHECK-SD-NEXT:    eor x0, x8, #0x7fffffff
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: selecti32i64:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov x8, #-2147483648 // =0xffffffff80000000
+; CHECK-GI-NEXT:    mov w9, #2147483647 // =0x7fffffff
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csel x0, x9, x8, ge
+; CHECK-GI-NEXT:    ret
   %c = icmp sgt i32 %a, -1
   %s = select i1 %c, i64 2147483647, i64 -2147483648
   ret i64 %s
@@ -62,45 +88,77 @@ define i8 @xori32i8(i32 %a) {
 }
 
 define i32 @selecti32i32(i32 %a) {
-; CHECK-LABEL: selecti32i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #84 // =0x54
-; CHECK-NEXT:    eor w0, w8, w0, asr #31
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: selecti32i32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #84 // =0x54
+; CHECK-SD-NEXT:    eor w0, w8, w0, asr #31
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: selecti32i32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #-85 // =0xffffffab
+; CHECK-GI-NEXT:    mov w9, #84 // =0x54
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csel w0, w9, w8, ge
+; CHECK-GI-NEXT:    ret
   %c = icmp sgt i32 %a, -1
   %s = select i1 %c, i32 84, i32 -85
   ret i32 %s
 }
 
 define i8 @selecti32i8(i32 %a) {
-; CHECK-LABEL: selecti32i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #84 // =0x54
-; CHECK-NEXT:    eor w0, w8, w0, asr #31
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: selecti32i8:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #84 // =0x54
+; CHECK-SD-NEXT:    eor w0, w8, w0, asr #31
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: selecti32i8:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #84 // =0x54
+; CHECK-GI-NEXT:    mov w9, #-85 // =0xffffffab
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csel w0, w8, w9, ge
+; CHECK-GI-NEXT:    ret
   %c = icmp sgt i32 %a, -1
   %s = select i1 %c, i8 84, i8 -85
   ret i8 %s
 }
 
 define i32 @selecti8i32(i8 %a) {
-; CHECK-LABEL: selecti8i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    sxtb w8, w0
-; CHECK-NEXT:    mov w9, #84 // =0x54
-; CHECK-NEXT:    eor w0, w9, w8, asr #7
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: selecti8i32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    sxtb w8, w0
+; CHECK-SD-NEXT:    mov w9, #84 // =0x54
+; CHECK-SD-NEXT:    eor w0, w9, w8, asr #7
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: selecti8i32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    sxtb w8, w0
+; CHECK-GI-NEXT:    mov w9, #-85 // =0xffffffab
+; CHECK-GI-NEXT:    mov w10, #84 // =0x54
+; CHECK-GI-NEXT:    cmp w8, #0
+; CHECK-GI-NEXT:    csel w0, w10, w9, ge
+; CHECK-GI-NEXT:    ret
   %c = icmp sgt i8 %a, -1
   %s = select i1 %c, i32 84, i32 -85
   ret i32 %s
 }
 
 define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
-; CHECK-LABEL: icmpasreq:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmp w0, #0
-; CHECK-NEXT:    csel w0, w1, w2, lt
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: icmpasreq:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmp w0, #0
+; CHECK-SD-NEXT:    csel w0, w1, w2, lt
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: icmpasreq:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #-1 // =0xffffffff
+; CHECK-GI-NEXT:    cmp w8, w0, asr #31
+; CHECK-GI-NEXT:    csel w0, w1, w2, eq
+; CHECK-GI-NEXT:    ret
   %sh = ashr i32 %input, 31
   %c = icmp eq i32 %sh, -1
   %s = select i1 %c, i32 %a, i32 %b
@@ -108,11 +166,18 @@ define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
 }
 
 define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
-; CHECK-LABEL: icmpasrne:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmp w0, #0
-; CHECK-NEXT:    csel w0, w1, w2, ge
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: icmpasrne:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmp w0, #0
+; CHECK-SD-NEXT:    csel w0, w1, w2, ge
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: icmpasrne:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #-1 // =0xffffffff
+; CHECK-GI-NEXT:    cmp w8, w0, asr #31
+; CHECK-GI-NEXT:    csel w0, w1, w2, ne
+; CHECK-GI-NEXT:    ret
   %sh = ashr i32 %input, 31
   %c = icmp ne i32 %sh, -1
   %s = select i1 %c, i32 %a, i32 %b
@@ -120,90 +185,153 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
 }
 
 define i32 @selecti32i32_0(i32 %a) {
-; CHECK-LABEL: selecti32i32_0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    asr w0, w0, #31
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: selecti32i32_0:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    asr w0, w0, #31
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: selecti32i32_0:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    cset w8, lt
+; CHECK-GI-NEXT:    sbfx w0, w8, #0, #1
+; CHECK-GI-NEXT:    ret
   %c = icmp sgt i32 %a, -1
   %s = select i1 %c, i32 0, i32 -1
   ret i32 %s
 }
 
 define i32 @selecti32i32_m1(i32 %a) {
-; CHECK-LABEL: selecti32i32_m1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mvn w8, w0
-; CHECK-NEXT:    asr w0, w8, #31
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: selecti32i32_m1:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mvn w8, w0
+; CHECK-SD-NEXT:    asr w0, w8, #31
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: selecti32i32_m1:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    cset w8, ge
+; CHECK-GI-NEXT:    sbfx w0, w8, #0, #1
+; CHECK-GI-NEXT:    ret
   %c = icmp sgt i32 %a, -1
   %s = select i1 %c, i32 -1, i32 0
   ret i32 %s
 }
 
 define i32 @selecti32i32_1(i32 %a) {
-; CHECK-LABEL: selecti32i32_1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    asr w8, w0, #31
-; CHECK-NEXT:    eor w0, w8, #0x1
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: selecti32i32_1:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    asr w8, w0, #31
+; CHECK-SD-NEXT:    eor w0, w8, #0x1
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: selecti32i32_1:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #-2 // =0xfffffffe
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csinc w0, w8, wzr, lt
+; CHECK-GI-NEXT:    ret
   %c = icmp sgt i32 %a, -1
   %s = select i1 %c, i32 1, i32 -2
   ret i32 %s
 }
 
 define i32 @selecti32i32_sge(i32 %a) {
-; CHECK-LABEL: selecti32i32_sge:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    asr w8, w0, #31
-; CHECK-NEXT:    eor w0, w8, #0xc
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: selecti32i32_sge:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    asr w8, w0, #31
+; CHECK-SD-NEXT:    eor w0, w8, #0xc
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: selecti32i32_sge:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #-13 // =0xfffffff3
+; CHECK-GI-NEXT:    mov w9, #12 // =0xc
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csel w0, w9, w8, ge
+; CHECK-GI-NEXT:    ret
   %c = icmp sge i32 %a, 0
   %s = select i1 %c, i32 12, i32 -13
   ret i32 %s
 }
 
 define i32 @selecti32i32_slt(i32 %a) {
-; CHECK-LABEL: selecti32i32_slt:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    asr w8, w0, #31
-; CHECK-NEXT:    eor w0, w8, #0xc
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: selecti32i32_slt:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    asr w8, w0, #31
+; CHECK-SD-NEXT:    eor w0, w8, #0xc
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: selecti32i32_slt:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #12 // =0xc
+; CHECK-GI-NEXT:    mov w9, #-13 // =0xfffffff3
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csel w0, w9, w8, lt
+; CHECK-GI-NEXT:    ret
   %c = icmp slt i32 %a, 0
   %s = select i1 %c, i32 -13, i32 12
   ret i32 %s
 }
 
 define i32 @selecti32i32_sle(i32 %a) {
-; CHECK-LABEL: selecti32i32_sle:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    asr w8, w0, #31
-; CHECK-NEXT:    eor w0, w8, #0xc
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: selecti32i32_sle:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    asr w8, w0, #31
+; CHECK-SD-NEXT:    eor w0, w8, #0xc
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: selecti32i32_sle:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #12 // =0xc
+; CHECK-GI-NEXT:    mov w9, #-13 // =0xfffffff3
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csel w0, w9, w8, lt
+; CHECK-GI-NEXT:    ret
   %c = icmp sle i32 %a, -1
   %s = select i1 %c, i32 -13, i32 12
   ret i32 %s
 }
 
 define i32 @selecti32i32_sgt(i32 %a) {
-; CHECK-LABEL: selecti32i32_sgt:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    asr w8, w0, #31
-; CHECK-NEXT:    eor w0, w8, #0xc
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: selecti32i32_sgt:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    asr w8, w0, #31
+; CHECK-SD-NEXT:    eor w0, w8, #0xc
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: selecti32i32_sgt:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #12 // =0xc
+; CHECK-GI-NEXT:    mov w9, #-13 // =0xfffffff3
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csel w0, w9, w8, lt
+; CHECK-GI-NEXT:    ret
   %c = icmp sle i32 %a, -1
   %s = select i1 %c, i32 -13, i32 12
   ret i32 %s
 }
 
 define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
-; CHECK-LABEL: oneusecmp:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    asr w8, w0, #31
-; CHECK-NEXT:    cmp w0, #0
-; CHECK-NEXT:    csel w9, w2, w1, lt
-; CHECK-NEXT:    eor w8, w8, #0x7f
-; CHECK-NEXT:    add w0, w8, w9
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: oneusecmp:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    asr w8, w0, #31
+; CHECK-SD-NEXT:    cmp w0, #0
+; CHECK-SD-NEXT:    csel w9, w2, w1, lt
+; CHECK-SD-NEXT:    eor w8, w8, #0x7f
+; CHECK-SD-NEXT:    add w0, w8, w9
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: oneusecmp:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #127 // =0x7f
+; CHECK-GI-NEXT:    mov w9, #-128 // =0xffffff80
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csel w8, w9, w8, lt
+; CHECK-GI-NEXT:    csel w9, w2, w1, lt
+; CHECK-GI-NEXT:    add w0, w8, w9
+; CHECK-GI-NEXT:    ret
   %c = icmp sle i32 %a, -1
   %s = select i1 %c, i32 -128, i32 127
   %s2 = select i1 %c, i32 %d, i32 %b

diff  --git a/llvm/test/CodeGen/AArch64/select-to-and-zext.ll b/llvm/test/CodeGen/AArch64/select-to-and-zext.ll
index 42a7c2114ed27..a980c960f8678 100644
--- a/llvm/test/CodeGen/AArch64/select-to-and-zext.ll
+++ b/llvm/test/CodeGen/AArch64/select-to-and-zext.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 define i32 @from_cmpeq(i32 %xx, i32 %y) {
 ; CHECK-LABEL: from_cmpeq:
@@ -29,22 +30,38 @@ define i32 @from_cmpeq_fail_bad_andmask(i32 %xx, i32 %y) {
 }
 
 define i32 @from_i1(i1 %x, i32 %y) {
-; CHECK-LABEL: from_i1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    and w8, w0, w1
-; CHECK-NEXT:    and w0, w8, #0x1
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: from_i1:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    and w8, w0, w1
+; CHECK-SD-NEXT:    and w0, w8, #0x1
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: from_i1:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    and w9, w1, #0x1
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, w9, wzr, ne
+; CHECK-GI-NEXT:    ret
   %masked = and i32 %y, 1
   %r = select i1 %x, i32 %masked, i32 0
   ret i32 %r
 }
 
 define i32 @from_trunc_i8(i8 %xx, i32 %y) {
-; CHECK-LABEL: from_trunc_i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    and w8, w0, w1
-; CHECK-NEXT:    and w0, w8, #0x1
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: from_trunc_i8:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    and w8, w0, w1
+; CHECK-SD-NEXT:    and w0, w8, #0x1
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: from_trunc_i8:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    and w9, w1, #0x1
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, w9, wzr, ne
+; CHECK-GI-NEXT:    ret
   %masked = and i32 %y, 1
   %x = trunc i8 %xx to i1
   %r = select i1 %x, i32 %masked, i32 0
@@ -52,11 +69,19 @@ define i32 @from_trunc_i8(i8 %xx, i32 %y) {
 }
 
 define i32 @from_trunc_i64(i64 %xx, i32 %y) {
-; CHECK-LABEL: from_trunc_i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    and w8, w0, w1
-; CHECK-NEXT:    and w0, w8, #0x1
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: from_trunc_i64:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    and w8, w0, w1
+; CHECK-SD-NEXT:    and w0, w8, #0x1
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: from_trunc_i64:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    and w9, w1, #0x1
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, w9, wzr, ne
+; CHECK-GI-NEXT:    ret
   %masked = and i32 %y, 1
   %x = trunc i64 %xx to i1
   %r = select i1 %x, i32 %masked, i32 0
@@ -64,24 +89,40 @@ define i32 @from_trunc_i64(i64 %xx, i32 %y) {
 }
 
 define i32 @from_i1_fail_bad_select0(i1 %x, i32 %y) {
-; CHECK-LABEL: from_i1_fail_bad_select0:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    and w8, w1, #0x1
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    csinc w0, w8, wzr, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: from_i1_fail_bad_select0:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    and w8, w1, #0x1
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    csinc w0, w8, wzr, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: from_i1_fail_bad_select0:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    and w9, w1, #0x1
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csinc w0, w9, wzr, ne
+; CHECK-GI-NEXT:    ret
   %masked = and i32 %y, 1
   %r = select i1 %x, i32 %masked, i32 1
   ret i32 %r
 }
 
 define i32 @from_i1_fail_bad_select1(i1 %x, i32 %y) {
-; CHECK-LABEL: from_i1_fail_bad_select1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    and w8, w1, #0x1
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    csel w0, wzr, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: from_i1_fail_bad_select1:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    and w8, w1, #0x1
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    csel w0, wzr, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: from_i1_fail_bad_select1:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    and w9, w1, #0x1
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, wzr, w9, ne
+; CHECK-GI-NEXT:    ret
   %masked = and i32 %y, 1
   %r = select i1 %x, i32 0, i32 %masked
   ret i32 %r

diff  --git a/llvm/test/CodeGen/AArch64/select-with-and-or.ll b/llvm/test/CodeGen/AArch64/select-with-and-or.ll
index 84b6818eaa739..60f2add81b45c 100644
--- a/llvm/test/CodeGen/AArch64/select-with-and-or.ll
+++ b/llvm/test/CodeGen/AArch64/select-with-and-or.ll
@@ -1,13 +1,23 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 define i1 @and(i32 %x, i32 %y, i32 %z, i32 %w) {
-; CHECK-LABEL: and:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmp w0, w1
-; CHECK-NEXT:    ccmp w2, w3, #4, eq
-; CHECK-NEXT:    cset w0, gt
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: and:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmp w0, w1
+; CHECK-SD-NEXT:    ccmp w2, w3, #4, eq
+; CHECK-SD-NEXT:    cset w0, gt
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: and:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmp w0, w1
+; CHECK-GI-NEXT:    cset w8, eq
+; CHECK-GI-NEXT:    cmp w2, w3
+; CHECK-GI-NEXT:    cset w9, gt
+; CHECK-GI-NEXT:    and w0, w8, w9
+; CHECK-GI-NEXT:    ret
   %a = icmp eq i32 %x, %y
   %b = icmp sgt i32 %z, %w
   %s = select i1 %a, i1 %b, i1 false
@@ -15,12 +25,22 @@ define i1 @and(i32 %x, i32 %y, i32 %z, i32 %w) {
 }
 
 define i1 @or(i32 %x, i32 %y, i32 %z, i32 %w) {
-; CHECK-LABEL: or:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmp w0, w1
-; CHECK-NEXT:    ccmp w2, w3, #0, ne
-; CHECK-NEXT:    cset w0, gt
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: or:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmp w0, w1
+; CHECK-SD-NEXT:    ccmp w2, w3, #0, ne
+; CHECK-SD-NEXT:    cset w0, gt
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: or:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmp w0, w1
+; CHECK-GI-NEXT:    cset w8, eq
+; CHECK-GI-NEXT:    cmp w2, w3
+; CHECK-GI-NEXT:    cset w9, gt
+; CHECK-GI-NEXT:    orr w8, w8, w9
+; CHECK-GI-NEXT:    and w0, w8, #0x1
+; CHECK-GI-NEXT:    ret
   %a = icmp eq i32 %x, %y
   %b = icmp sgt i32 %z, %w
   %s = select i1 %a, i1 true, i1 %b
@@ -28,12 +48,21 @@ define i1 @or(i32 %x, i32 %y, i32 %z, i32 %w) {
 }
 
 define i1 @and_not(i32 %x, i32 %y, i32 %z, i32 %w) {
-; CHECK-LABEL: and_not:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmp w0, w1
-; CHECK-NEXT:    ccmp w2, w3, #4, ne
-; CHECK-NEXT:    cset w0, gt
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: and_not:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmp w0, w1
+; CHECK-SD-NEXT:    ccmp w2, w3, #4, ne
+; CHECK-SD-NEXT:    cset w0, gt
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: and_not:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmp w0, w1
+; CHECK-GI-NEXT:    cset w8, ne
+; CHECK-GI-NEXT:    cmp w2, w3
+; CHECK-GI-NEXT:    cset w9, gt
+; CHECK-GI-NEXT:    and w0, w8, w9
+; CHECK-GI-NEXT:    ret
   %a = icmp eq i32 %x, %y
   %b = icmp sgt i32 %z, %w
   %s = select i1 %a, i1 false, i1 %b
@@ -41,12 +70,22 @@ define i1 @and_not(i32 %x, i32 %y, i32 %z, i32 %w) {
 }
 
 define i1 @or_not(i32 %x, i32 %y, i32 %z, i32 %w) {
-; CHECK-LABEL: or_not:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmp w0, w1
-; CHECK-NEXT:    ccmp w2, w3, #0, eq
-; CHECK-NEXT:    cset w0, gt
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: or_not:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmp w0, w1
+; CHECK-SD-NEXT:    ccmp w2, w3, #0, eq
+; CHECK-SD-NEXT:    cset w0, gt
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: or_not:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmp w0, w1
+; CHECK-GI-NEXT:    cset w8, ne
+; CHECK-GI-NEXT:    cmp w2, w3
+; CHECK-GI-NEXT:    cset w9, gt
+; CHECK-GI-NEXT:    orr w8, w8, w9
+; CHECK-GI-NEXT:    and w0, w8, #0x1
+; CHECK-GI-NEXT:    ret
   %a = icmp eq i32 %x, %y
   %b = icmp sgt i32 %z, %w
   %s = select i1 %a, i1 %b, i1 true
@@ -54,13 +93,21 @@ define i1 @or_not(i32 %x, i32 %y, i32 %z, i32 %w) {
 }
 
 define <4 x i1> @and_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
-; CHECK-LABEL: and_vec:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
-; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT:    xtn v0.4h, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: and_vec:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmgt v2.4s, v2.4s, v3.4s
+; CHECK-SD-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT:    and v0.16b, v0.16b, v2.16b
+; CHECK-SD-NEXT:    xtn v0.4h, v0.4s
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: and_vec:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT:    cmgt v1.4s, v2.4s, v3.4s
+; CHECK-GI-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT:    xtn v0.4h, v0.4s
+; CHECK-GI-NEXT:    ret
   %a = icmp eq <4 x i32> %x, %y
   %b = icmp sgt <4 x i32> %z, %w
   %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> zeroinitializer
@@ -68,13 +115,21 @@ define <4 x i1> @and_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w)
 }
 
 define <4 x i1> @or_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
-; CHECK-LABEL: or_vec:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
-; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
-; CHECK-NEXT:    xtn v0.4h, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: or_vec:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmgt v2.4s, v2.4s, v3.4s
+; CHECK-SD-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT:    orr v0.16b, v0.16b, v2.16b
+; CHECK-SD-NEXT:    xtn v0.4h, v0.4s
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: or_vec:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT:    cmgt v1.4s, v2.4s, v3.4s
+; CHECK-GI-NEXT:    orr v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT:    xtn v0.4h, v0.4s
+; CHECK-GI-NEXT:    ret
   %a = icmp eq <4 x i32> %x, %y
   %b = icmp sgt <4 x i32> %z, %w
   %s = select <4 x i1> %a, <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1> %b
@@ -82,13 +137,21 @@ define <4 x i1> @or_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w)
 }
 
 define <4 x i1> @and_not_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
-; CHECK-LABEL: and_not_vec:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
-; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    bic v0.16b, v2.16b, v0.16b
-; CHECK-NEXT:    xtn v0.4h, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: and_not_vec:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmgt v2.4s, v2.4s, v3.4s
+; CHECK-SD-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT:    bic v0.16b, v2.16b, v0.16b
+; CHECK-SD-NEXT:    xtn v0.4h, v0.4s
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: and_not_vec:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT:    cmgt v1.4s, v2.4s, v3.4s
+; CHECK-GI-NEXT:    bic v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT:    xtn v0.4h, v0.4s
+; CHECK-GI-NEXT:    ret
   %a = icmp eq <4 x i32> %x, %y
   %b = icmp sgt <4 x i32> %z, %w
   %s = select <4 x i1> %a, <4 x i1> zeroinitializer, <4 x i1> %b
@@ -96,13 +159,21 @@ define <4 x i1> @and_not_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32>
 }
 
 define <4 x i1> @or_not_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
-; CHECK-LABEL: or_not_vec:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
-; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    orn v0.16b, v2.16b, v0.16b
-; CHECK-NEXT:    xtn v0.4h, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: or_not_vec:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmgt v2.4s, v2.4s, v3.4s
+; CHECK-SD-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT:    orn v0.16b, v2.16b, v0.16b
+; CHECK-SD-NEXT:    xtn v0.4h, v0.4s
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: or_not_vec:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT:    cmgt v1.4s, v2.4s, v3.4s
+; CHECK-GI-NEXT:    orn v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT:    xtn v0.4h, v0.4s
+; CHECK-GI-NEXT:    ret
   %a = icmp eq <4 x i32> %x, %y
   %b = icmp sgt <4 x i32> %z, %w
   %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> <i1 1, i1 1, i1 1, i1 1>
@@ -110,13 +181,21 @@ define <4 x i1> @or_not_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32>
 }
 
 define <4 x i1> @and_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
-; CHECK-LABEL: and_vec_undef:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
-; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT:    xtn v0.4h, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: and_vec_undef:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmgt v2.4s, v2.4s, v3.4s
+; CHECK-SD-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT:    and v0.16b, v0.16b, v2.16b
+; CHECK-SD-NEXT:    xtn v0.4h, v0.4s
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: and_vec_undef:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT:    cmgt v1.4s, v2.4s, v3.4s
+; CHECK-GI-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT:    xtn v0.4h, v0.4s
+; CHECK-GI-NEXT:    ret
   %a = icmp eq <4 x i32> %x, %y
   %b = icmp sgt <4 x i32> %z, %w
   %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> <i1 0, i1 undef, i1 0, i1 undef>
@@ -124,13 +203,21 @@ define <4 x i1> @and_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i3
 }
 
 define <4 x i1> @or_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
-; CHECK-LABEL: or_vec_undef:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
-; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    orr v0.16b, v0.16b, v2.16b
-; CHECK-NEXT:    xtn v0.4h, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: or_vec_undef:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmgt v2.4s, v2.4s, v3.4s
+; CHECK-SD-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT:    orr v0.16b, v0.16b, v2.16b
+; CHECK-SD-NEXT:    xtn v0.4h, v0.4s
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: or_vec_undef:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT:    cmgt v1.4s, v2.4s, v3.4s
+; CHECK-GI-NEXT:    orr v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT:    xtn v0.4h, v0.4s
+; CHECK-GI-NEXT:    ret
   %a = icmp eq <4 x i32> %x, %y
   %b = icmp sgt <4 x i32> %z, %w
   %s = select <4 x i1> %a, <4 x i1> <i1 undef, i1 1, i1 1, i1 undef>, <4 x i1> %b
@@ -138,13 +225,21 @@ define <4 x i1> @or_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32
 }
 
 define <4 x i1> @and_not_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
-; CHECK-LABEL: and_not_vec_undef:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
-; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    bic v0.16b, v2.16b, v0.16b
-; CHECK-NEXT:    xtn v0.4h, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: and_not_vec_undef:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmgt v2.4s, v2.4s, v3.4s
+; CHECK-SD-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT:    bic v0.16b, v2.16b, v0.16b
+; CHECK-SD-NEXT:    xtn v0.4h, v0.4s
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: and_not_vec_undef:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT:    cmgt v1.4s, v2.4s, v3.4s
+; CHECK-GI-NEXT:    bic v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT:    xtn v0.4h, v0.4s
+; CHECK-GI-NEXT:    ret
   %a = icmp eq <4 x i32> %x, %y
   %b = icmp sgt <4 x i32> %z, %w
   %s = select <4 x i1> %a, <4 x i1> <i1 0, i1 0, i1 undef, i1 0>, <4 x i1> %b
@@ -152,15 +247,25 @@ define <4 x i1> @and_not_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4
 }
 
 define <4 x i1> @or_not_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
-; CHECK-LABEL: or_not_vec_undef:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmgt v2.4s, v2.4s, v3.4s
-; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    orn v0.16b, v2.16b, v0.16b
-; CHECK-NEXT:    xtn v0.4h, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: or_not_vec_undef:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    cmgt v2.4s, v2.4s, v3.4s
+; CHECK-SD-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT:    orn v0.16b, v2.16b, v0.16b
+; CHECK-SD-NEXT:    xtn v0.4h, v0.4s
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: or_not_vec_undef:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT:    cmgt v1.4s, v2.4s, v3.4s
+; CHECK-GI-NEXT:    orn v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT:    xtn v0.4h, v0.4s
+; CHECK-GI-NEXT:    ret
   %a = icmp eq <4 x i32> %x, %y
   %b = icmp sgt <4 x i32> %z, %w
   %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> <i1 1, i1 undef, i1 1, i1 1>
   ret <4 x i1> %s
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}

diff  --git a/llvm/test/CodeGen/AArch64/select_cc.ll b/llvm/test/CodeGen/AArch64/select_cc.ll
index 92c8087518151..6a00878ffea7a 100644
--- a/llvm/test/CodeGen/AArch64/select_cc.ll
+++ b/llvm/test/CodeGen/AArch64/select_cc.ll
@@ -1,13 +1,21 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 define i64 @select_ogt_float(float %a, float %b) {
-; CHECK-LABEL: select_ogt_float:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    cset w8, gt
-; CHECK-NEXT:    ubfiz x0, x8, #2, #32
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_ogt_float:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    fcmp s0, s1
+; CHECK-SD-NEXT:    cset w8, gt
+; CHECK-SD-NEXT:    ubfiz x0, x8, #2, #32
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_ogt_float:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    fcmp s0, s1
+; CHECK-GI-NEXT:    cset w8, gt
+; CHECK-GI-NEXT:    lsl x0, x8, #2
+; CHECK-GI-NEXT:    ret
 entry:
   %cc = fcmp ogt float %a, %b
   %sel = select i1 %cc, i64 4, i64 0
@@ -15,12 +23,19 @@ entry:
 }
 
 define i64 @select_ule_float_inverse(float %a, float %b) {
-; CHECK-LABEL: select_ule_float_inverse:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    cset w8, gt
-; CHECK-NEXT:    ubfiz x0, x8, #2, #32
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_ule_float_inverse:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    fcmp s0, s1
+; CHECK-SD-NEXT:    cset w8, gt
+; CHECK-SD-NEXT:    ubfiz x0, x8, #2, #32
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_ule_float_inverse:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    fcmp s0, s1
+; CHECK-GI-NEXT:    cset w8, gt
+; CHECK-GI-NEXT:    lsl x0, x8, #2
+; CHECK-GI-NEXT:    ret
 entry:
   %cc = fcmp ule float %a, %b
   %sel = select i1 %cc, i64 0, i64 4
@@ -28,12 +43,19 @@ entry:
 }
 
 define i64 @select_eq_i32(i32 %a, i32 %b) {
-; CHECK-LABEL: select_eq_i32:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    cmp w0, w1
-; CHECK-NEXT:    cset w8, eq
-; CHECK-NEXT:    ubfiz x0, x8, #2, #32
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_eq_i32:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    cmp w0, w1
+; CHECK-SD-NEXT:    cset w8, eq
+; CHECK-SD-NEXT:    ubfiz x0, x8, #2, #32
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_eq_i32:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    cmp w0, w1
+; CHECK-GI-NEXT:    cset w8, eq
+; CHECK-GI-NEXT:    lsl x0, x8, #2
+; CHECK-GI-NEXT:    ret
 entry:
   %cc = icmp eq i32 %a, %b
   %sel = select i1 %cc, i64 4, i64 0
@@ -41,12 +63,19 @@ entry:
 }
 
 define i64 @select_ne_i32_inverse(i32 %a, i32 %b) {
-; CHECK-LABEL: select_ne_i32_inverse:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    cmp w0, w1
-; CHECK-NEXT:    cset w8, eq
-; CHECK-NEXT:    ubfiz x0, x8, #2, #32
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_ne_i32_inverse:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    cmp w0, w1
+; CHECK-SD-NEXT:    cset w8, eq
+; CHECK-SD-NEXT:    ubfiz x0, x8, #2, #32
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_ne_i32_inverse:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    cmp w0, w1
+; CHECK-GI-NEXT:    cset w8, eq
+; CHECK-GI-NEXT:    lsl x0, x8, #2
+; CHECK-GI-NEXT:    ret
 entry:
   %cc = icmp ne i32 %a, %b
   %sel = select i1 %cc, i64 0, i64 4
@@ -54,14 +83,25 @@ entry:
 }
 
 define <2 x double> @select_olt_load_cmp(<2 x double> %a, ptr %src) {
-; CHECK-LABEL: select_olt_load_cmp:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi d1, #0000000000000000
-; CHECK-NEXT:    ldr d2, [x0]
-; CHECK-NEXT:    fcmgt v1.2s, v2.2s, v1.2s
-; CHECK-NEXT:    sshll v1.2d, v1.2s, #0
-; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_olt_load_cmp:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    movi d1, #0000000000000000
+; CHECK-SD-NEXT:    ldr d2, [x0]
+; CHECK-SD-NEXT:    fcmgt v1.2s, v2.2s, v1.2s
+; CHECK-SD-NEXT:    sshll v1.2d, v1.2s, #0
+; CHECK-SD-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_olt_load_cmp:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    ldr d1, [x0]
+; CHECK-GI-NEXT:    movi v2.2d, #0000000000000000
+; CHECK-GI-NEXT:    fcmgt v1.2s, v1.2s, #0.0
+; CHECK-GI-NEXT:    ushll v1.2d, v1.2s, #0
+; CHECK-GI-NEXT:    shl v1.2d, v1.2d, #63
+; CHECK-GI-NEXT:    sshr v1.2d, v1.2d, #63
+; CHECK-GI-NEXT:    bif v0.16b, v2.16b, v1.16b
+; CHECK-GI-NEXT:    ret
 entry:
   %l = load <2 x float>, ptr %src, align 4
   %cmp = fcmp olt <2 x float> zeroinitializer, %l
@@ -70,16 +110,40 @@ entry:
 }
 
 define <4 x i32> @select_icmp_sgt(<4 x i32> %a, <4 x i8> %b) {
-; CHECK-LABEL: select_icmp_sgt:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    shl v1.4h, v1.4h, #8
-; CHECK-NEXT:    sshr v1.4h, v1.4h, #8
-; CHECK-NEXT:    cmgt v1.4h, v1.4h, #0
-; CHECK-NEXT:    sshll v1.4s, v1.4h, #0
-; CHECK-NEXT:    bic v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_icmp_sgt:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    shl v1.4h, v1.4h, #8
+; CHECK-SD-NEXT:    sshr v1.4h, v1.4h, #8
+; CHECK-SD-NEXT:    cmgt v1.4h, v1.4h, #0
+; CHECK-SD-NEXT:    sshll v1.4s, v1.4h, #0
+; CHECK-SD-NEXT:    bic v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_icmp_sgt:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    mov w8, #0 // =0x0
+; CHECK-GI-NEXT:    uzp1 v1.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT:    fmov s2, w8
+; CHECK-GI-NEXT:    mov v2.b[1], w8
+; CHECK-GI-NEXT:    mov v2.b[2], w8
+; CHECK-GI-NEXT:    mov v2.b[3], w8
+; CHECK-GI-NEXT:    cmgt v1.8b, v1.8b, v2.8b
+; CHECK-GI-NEXT:    umov w8, v1.b[0]
+; CHECK-GI-NEXT:    umov w9, v1.b[1]
+; CHECK-GI-NEXT:    mov v2.s[0], w8
+; CHECK-GI-NEXT:    umov w8, v1.b[2]
+; CHECK-GI-NEXT:    mov v2.s[1], w9
+; CHECK-GI-NEXT:    umov w9, v1.b[3]
+; CHECK-GI-NEXT:    mov v2.s[2], w8
+; CHECK-GI-NEXT:    mov v2.s[3], w9
+; CHECK-GI-NEXT:    shl v1.4s, v2.4s, #31
+; CHECK-GI-NEXT:    sshr v1.4s, v1.4s, #31
+; CHECK-GI-NEXT:    bic v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT:    ret
 entry:
   %cmp = icmp sgt <4 x i8> %b, zeroinitializer
   %sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %a
   ret <4 x i32> %sel
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}

diff  --git a/llvm/test/CodeGen/AArch64/select_const.ll b/llvm/test/CodeGen/AArch64/select_const.ll
index cd50d776e913f..801093daef70d 100644
--- a/llvm/test/CodeGen/AArch64/select_const.ll
+++ b/llvm/test/CodeGen/AArch64/select_const.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 ; Select of constants: control flow / conditional moves can always be replaced by logic+math (but may not be worth it?).
 ; Test the zeroext/signext variants of each pattern to see if that makes a 
diff erence.
@@ -7,11 +8,17 @@
 ; select Cond, 0, 1 --> zext (!Cond)
 
 define i32 @select_0_or_1(i1 %cond) {
-; CHECK-LABEL: select_0_or_1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1 // =0x1
-; CHECK-NEXT:    bic w0, w8, w0
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_0_or_1:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #1 // =0x1
+; CHECK-SD-NEXT:    bic w0, w8, w0
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_0_or_1:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    eor w8, w0, #0x1
+; CHECK-GI-NEXT:    and w0, w8, #0x1
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 0, i32 1
   ret i32 %sel
 }
@@ -26,11 +33,17 @@ define i32 @select_0_or_1_zeroext(i1 zeroext %cond) {
 }
 
 define i32 @select_0_or_1_signext(i1 signext %cond) {
-; CHECK-LABEL: select_0_or_1_signext:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #1 // =0x1
-; CHECK-NEXT:    bic w0, w8, w0
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_0_or_1_signext:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #1 // =0x1
+; CHECK-SD-NEXT:    bic w0, w8, w0
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_0_or_1_signext:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    eor w8, w0, #0x1
+; CHECK-GI-NEXT:    and w0, w8, #0x1
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 0, i32 1
   ret i32 %sel
 }
@@ -66,29 +79,47 @@ define i32 @select_1_or_0_signext(i1 signext %cond) {
 ; select Cond, 0, -1 --> sext (!Cond)
 
 define i32 @select_0_or_neg1(i1 %cond) {
-; CHECK-LABEL: select_0_or_neg1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    and w8, w0, #0x1
-; CHECK-NEXT:    sub w0, w8, #1
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_0_or_neg1:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    and w8, w0, #0x1
+; CHECK-SD-NEXT:    sub w0, w8, #1
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_0_or_neg1:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    eor w8, w0, #0x1
+; CHECK-GI-NEXT:    sbfx w0, w8, #0, #1
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 0, i32 -1
   ret i32 %sel
 }
 
 define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
-; CHECK-LABEL: select_0_or_neg1_zeroext:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub w0, w0, #1
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_0_or_neg1_zeroext:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    sub w0, w0, #1
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_0_or_neg1_zeroext:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    eor w8, w0, #0x1
+; CHECK-GI-NEXT:    sbfx w0, w8, #0, #1
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 0, i32 -1
   ret i32 %sel
 }
 
 define i32 @select_0_or_neg1_signext(i1 signext %cond) {
-; CHECK-LABEL: select_0_or_neg1_signext:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mvn w0, w0
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_0_or_neg1_signext:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mvn w0, w0
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_0_or_neg1_signext:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    eor w8, w0, #0x1
+; CHECK-GI-NEXT:    sbfx w0, w8, #0, #1
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 0, i32 -1
   ret i32 %sel
 }
@@ -124,34 +155,51 @@ define i32 @select_neg1_or_0_signext(i1 signext %cond) {
 ; select Cond, C+1, C --> add (zext Cond), C
 
 define i32 @select_Cplus1_C(i1 %cond) {
-; CHECK-LABEL: select_Cplus1_C:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #41 // =0x29
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    cinc w0, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_Cplus1_C:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #41 // =0x29
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    cinc w0, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_Cplus1_C:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    add w0, w8, #41
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 42, i32 41
   ret i32 %sel
 }
 
 define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {
-; CHECK-LABEL: select_Cplus1_C_zeroext:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #41 // =0x29
-; CHECK-NEXT:    cmp w0, #0
-; CHECK-NEXT:    cinc w0, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_Cplus1_C_zeroext:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #41 // =0x29
+; CHECK-SD-NEXT:    cmp w0, #0
+; CHECK-SD-NEXT:    cinc w0, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_Cplus1_C_zeroext:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    add w0, w0, #41
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 42, i32 41
   ret i32 %sel
 }
 
 define i32 @select_Cplus1_C_signext(i1 signext %cond) {
-; CHECK-LABEL: select_Cplus1_C_signext:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #41 // =0x29
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    cinc w0, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_Cplus1_C_signext:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #41 // =0x29
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    cinc w0, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_Cplus1_C_signext:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    add w0, w8, #41
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 42, i32 41
   ret i32 %sel
 }
@@ -159,34 +207,51 @@ define i32 @select_Cplus1_C_signext(i1 signext %cond) {
 ; select Cond, C, C+1 --> add (sext Cond), C
 
 define i32 @select_C_Cplus1(i1 %cond) {
-; CHECK-LABEL: select_C_Cplus1:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #41 // =0x29
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    cinc w0, w8, eq
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_C_Cplus1:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #41 // =0x29
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    cinc w0, w8, eq
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_C_Cplus1:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    sbfx w8, w0, #0, #1
+; CHECK-GI-NEXT:    add w0, w8, #42
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
-; CHECK-LABEL: select_C_Cplus1_zeroext:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #41 // =0x29
-; CHECK-NEXT:    cmp w0, #0
-; CHECK-NEXT:    cinc w0, w8, eq
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_C_Cplus1_zeroext:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #41 // =0x29
+; CHECK-SD-NEXT:    cmp w0, #0
+; CHECK-SD-NEXT:    cinc w0, w8, eq
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_C_Cplus1_zeroext:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    sbfx w8, w0, #0, #1
+; CHECK-GI-NEXT:    add w0, w8, #42
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C_Cplus1_signext(i1 signext %cond) {
-; CHECK-LABEL: select_C_Cplus1_signext:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #41 // =0x29
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    cinc w0, w8, eq
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_C_Cplus1_signext:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #41 // =0x29
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    cinc w0, w8, eq
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_C_Cplus1_signext:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    add w0, w0, #42
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
@@ -195,37 +260,63 @@ define i32 @select_C_Cplus1_signext(i1 signext %cond) {
 ; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2
 
 define i32 @select_C1_C2(i1 %cond) {
-; CHECK-LABEL: select_C1_C2:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #42 // =0x2a
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #421 // =0x1a5
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_C1_C2:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #42 // =0x2a
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #421 // =0x1a5
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_C1_C2:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    mov w9, #42 // =0x2a
+; CHECK-GI-NEXT:    mov w10, #421 // =0x1a5
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, w10, w9, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 421, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
-; CHECK-LABEL: select_C1_C2_zeroext:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #42 // =0x2a
-; CHECK-NEXT:    cmp w0, #0
-; CHECK-NEXT:    mov w9, #421 // =0x1a5
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_C1_C2_zeroext:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #42 // =0x2a
+; CHECK-SD-NEXT:    cmp w0, #0
+; CHECK-SD-NEXT:    mov w9, #421 // =0x1a5
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_C1_C2_zeroext:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #42 // =0x2a
+; CHECK-GI-NEXT:    mov w9, #421 // =0x1a5
+; CHECK-GI-NEXT:    tst w0, #0x1
+; CHECK-GI-NEXT:    csel w0, w9, w8, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 421, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C1_C2_signext(i1 signext %cond) {
-; CHECK-LABEL: select_C1_C2_signext:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #42 // =0x2a
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #421 // =0x1a5
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_C1_C2_signext:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #42 // =0x2a
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #421 // =0x1a5
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_C1_C2_signext:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    mov w9, #42 // =0x2a
+; CHECK-GI-NEXT:    mov w10, #421 // =0x1a5
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, w10, w9, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i32 421, i32 42
   ret i32 %sel
 }
@@ -233,239 +324,404 @@ define i32 @select_C1_C2_signext(i1 signext %cond) {
 ; A binary operator with constant after the select should always get folded into the select.
 
 define i8 @sel_constants_add_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_add_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #28 // =0x1c
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    csinc w0, w8, wzr, eq
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_add_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #28 // =0x1c
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    csinc w0, w8, wzr, eq
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_add_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w9, w0, #0x1
+; CHECK-GI-NEXT:    mov w8, #28 // =0x1c
+; CHECK-GI-NEXT:    tst w9, #0x1
+; CHECK-GI-NEXT:    csinc w0, w8, wzr, eq
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = add i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sub_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_sub_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #18 // =0x12
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #-9 // =0xfffffff7
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_sub_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #18 // =0x12
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #-9 // =0xfffffff7
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_sub_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    mov w9, #-9 // =0xfffffff7
+; CHECK-GI-NEXT:    mov w10, #18 // =0x12
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, w9, w10, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = sub i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sub_constant_sel_constants(i1 %cond) {
-; CHECK-LABEL: sel_constants_sub_constant_sel_constants:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #2 // =0x2
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #9 // =0x9
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_sub_constant_sel_constants:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #2 // =0x2
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #9 // =0x9
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_sub_constant_sel_constants:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    mov w9, #9 // =0x9
+; CHECK-GI-NEXT:    mov w10, #2 // =0x2
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, w9, w10, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 3
   %bo = sub i8 5, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_mul_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_mul_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #115 // =0x73
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #-20 // =0xffffffec
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_mul_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #115 // =0x73
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #-20 // =0xffffffec
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_mul_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    mov w9, #-4 // =0xfffffffc
+; CHECK-GI-NEXT:    mov w10, #23 // =0x17
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w8, w9, w10, ne
+; CHECK-GI-NEXT:    add w0, w8, w8, lsl #2
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = mul i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sdiv_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_sdiv_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #4 // =0x4
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    csel w0, wzr, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_sdiv_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #4 // =0x4
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    csel w0, wzr, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_sdiv_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    eor w8, w0, #0x1
+; CHECK-GI-NEXT:    and w8, w8, #0x1
+; CHECK-GI-NEXT:    lsl w0, w8, #2
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = sdiv i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sdiv_constant_sel_constants(i1 %cond) {
-; CHECK-LABEL: sdiv_constant_sel_constants:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #5 // =0x5
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    csel w0, wzr, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sdiv_constant_sel_constants:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #5 // =0x5
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    csel w0, wzr, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sdiv_constant_sel_constants:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w9, w0, #0x1
+; CHECK-GI-NEXT:    mov w8, #5 // =0x5
+; CHECK-GI-NEXT:    tst w9, #0x1
+; CHECK-GI-NEXT:    csel w0, wzr, w8, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 121, i8 23
   %bo = sdiv i8 120, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_udiv_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_udiv_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #4 // =0x4
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #50 // =0x32
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_udiv_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #4 // =0x4
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #50 // =0x32
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_udiv_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    mov w9, #-4 // =0xfffffffc
+; CHECK-GI-NEXT:    mov w10, #23 // =0x17
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w8, w9, w10, ne
+; CHECK-GI-NEXT:    mov w9, #205 // =0xcd
+; CHECK-GI-NEXT:    and w8, w8, #0xff
+; CHECK-GI-NEXT:    mul w8, w8, w9
+; CHECK-GI-NEXT:    lsr w8, w8, #8
+; CHECK-GI-NEXT:    lsr w0, w8, #2
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = udiv i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @udiv_constant_sel_constants(i1 %cond) {
-; CHECK-LABEL: udiv_constant_sel_constants:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #5 // =0x5
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    csel w0, wzr, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: udiv_constant_sel_constants:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #5 // =0x5
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    csel w0, wzr, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: udiv_constant_sel_constants:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w9, w0, #0x1
+; CHECK-GI-NEXT:    mov w8, #5 // =0x5
+; CHECK-GI-NEXT:    tst w9, #0x1
+; CHECK-GI-NEXT:    csel w0, wzr, w8, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = udiv i8 120, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_srem_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_srem_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-4 // =0xfffffffc
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    cinv w0, w8, eq
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_srem_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #-4 // =0xfffffffc
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    cinv w0, w8, eq
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_srem_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    mov w9, #-4 // =0xfffffffc
+; CHECK-GI-NEXT:    mov w10, #3 // =0x3
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, w9, w10, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = srem i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @srem_constant_sel_constants(i1 %cond) {
-; CHECK-LABEL: srem_constant_sel_constants:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #5 // =0x5
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #120 // =0x78
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: srem_constant_sel_constants:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #5 // =0x5
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #120 // =0x78
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: srem_constant_sel_constants:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    mov w9, #120 // =0x78
+; CHECK-GI-NEXT:    mov w10, #5 // =0x5
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, w9, w10, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 121, i8 23
   %bo = srem i8 120, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_urem_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_urem_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #2 // =0x2
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    cinc w0, w8, eq
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_urem_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #2 // =0x2
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    cinc w0, w8, eq
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_urem_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    sbfx w8, w0, #0, #1
+; CHECK-GI-NEXT:    add w0, w8, #3
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = urem i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @urem_constant_sel_constants(i1 %cond) {
-; CHECK-LABEL: urem_constant_sel_constants:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #5 // =0x5
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #120 // =0x78
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: urem_constant_sel_constants:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #5 // =0x5
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #120 // =0x78
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: urem_constant_sel_constants:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    mov w9, #120 // =0x78
+; CHECK-GI-NEXT:    mov w10, #5 // =0x5
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, w9, w10, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = urem i8 120, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_and_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_and_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #4 // =0x4
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    cinc w0, w8, eq
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_and_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #4 // =0x4
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    cinc w0, w8, eq
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_and_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    sbfx w8, w0, #0, #1
+; CHECK-GI-NEXT:    add w0, w8, #5
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = and i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_or_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_or_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #23 // =0x17
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #-3 // =0xfffffffd
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_or_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #23 // =0x17
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #-3 // =0xfffffffd
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_or_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    mov w9, #-3 // =0xfffffffd
+; CHECK-GI-NEXT:    mov w10, #23 // =0x17
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, w9, w10, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = or i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_xor_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_xor_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #18 // =0x12
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #-7 // =0xfffffff9
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_xor_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #18 // =0x12
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #-7 // =0xfffffff9
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_xor_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    mov w9, #-7 // =0xfffffff9
+; CHECK-GI-NEXT:    mov w10, #18 // =0x12
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, w9, w10, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = xor i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_shl_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_shl_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-32 // =0xffffffe0
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #-128 // =0xffffff80
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_shl_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #-32 // =0xffffffe0
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #-128 // =0xffffff80
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_shl_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    mov w9, #-128 // =0xffffff80
+; CHECK-GI-NEXT:    mov w10, #-32 // =0xffffffe0
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    csel w0, w9, w10, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = shl i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @shl_constant_sel_constants(i1 %cond) {
-; CHECK-LABEL: shl_constant_sel_constants:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #8 // =0x8
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #4 // =0x4
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: shl_constant_sel_constants:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #8 // =0x8
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #4 // =0x4
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: shl_constant_sel_constants:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    sbfx w9, w0, #0, #1
+; CHECK-GI-NEXT:    mov w8, #1 // =0x1
+; CHECK-GI-NEXT:    add w9, w9, #3
+; CHECK-GI-NEXT:    and w9, w9, #0xff
+; CHECK-GI-NEXT:    lsl w0, w8, w9
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 2, i8 3
   %bo = shl i8 1, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_lshr_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_lshr_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #7 // =0x7
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    csel w0, w8, wzr, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_lshr_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #7 // =0x7
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    csel w0, w8, wzr, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_lshr_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w9, w0, #0x1
+; CHECK-GI-NEXT:    mov w8, #7 // =0x7
+; CHECK-GI-NEXT:    tst w9, #0x1
+; CHECK-GI-NEXT:    csel w0, w8, wzr, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = lshr i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @lshr_constant_sel_constants(i1 %cond) {
-; CHECK-LABEL: lshr_constant_sel_constants:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #8 // =0x8
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #16 // =0x10
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: lshr_constant_sel_constants:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #8 // =0x8
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #16 // =0x10
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: lshr_constant_sel_constants:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    sbfx w9, w0, #0, #1
+; CHECK-GI-NEXT:    mov w8, #64 // =0x40
+; CHECK-GI-NEXT:    add w9, w9, #3
+; CHECK-GI-NEXT:    and w9, w9, #0xff
+; CHECK-GI-NEXT:    lsr w0, w8, w9
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 2, i8 3
   %bo = lshr i8 64, %sel
   ret i8 %bo
@@ -483,138 +739,240 @@ define i8 @sel_constants_ashr_constant(i1 %cond) {
 }
 
 define i8 @ashr_constant_sel_constants(i1 %cond) {
-; CHECK-LABEL: ashr_constant_sel_constants:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-16 // =0xfffffff0
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w9, #-32 // =0xffffffe0
-; CHECK-NEXT:    csel w0, w9, w8, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: ashr_constant_sel_constants:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #-16 // =0xfffffff0
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    mov w9, #-32 // =0xffffffe0
+; CHECK-SD-NEXT:    csel w0, w9, w8, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: ashr_constant_sel_constants:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    sbfx w9, w0, #0, #1
+; CHECK-GI-NEXT:    mov w8, #-128 // =0xffffff80
+; CHECK-GI-NEXT:    add w9, w9, #3
+; CHECK-GI-NEXT:    and w9, w9, #0xff
+; CHECK-GI-NEXT:    asr w0, w8, w9
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, i8 2, i8 3
   %bo = ashr i8 128, %sel
   ret i8 %bo
 }
 
 define double @sel_constants_fadd_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_fadd_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x9, #7378697629483820646 // =0x6666666666666666
-; CHECK-NEXT:    adrp x8, .LCPI42_0
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    movk x9, #16444, lsl #48
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI42_0]
-; CHECK-NEXT:    fmov d1, x9
-; CHECK-NEXT:    fcsel d0, d0, d1, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_fadd_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov x9, #7378697629483820646 // =0x6666666666666666
+; CHECK-SD-NEXT:    adrp x8, .LCPI42_0
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    movk x9, #16444, lsl #48
+; CHECK-SD-NEXT:    ldr d0, [x8, :lo12:.LCPI42_0]
+; CHECK-SD-NEXT:    fmov d1, x9
+; CHECK-SD-NEXT:    fcsel d0, d0, d1, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_fadd_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov x9, #7378697629483820646 // =0x6666666666666666
+; CHECK-GI-NEXT:    adrp x8, .LCPI42_0
+; CHECK-GI-NEXT:    movk x9, #16444, lsl #48
+; CHECK-GI-NEXT:    ldr d0, [x8, :lo12:.LCPI42_0]
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    fmov d1, x9
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    fcsel d0, d0, d1, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fadd double %sel, 5.1
   ret double %bo
 }
 
 define double @sel_constants_fsub_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_fsub_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI43_0
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI43_0]
-; CHECK-NEXT:    mov x8, #3689348814741910323 // =0x3333333333333333
-; CHECK-NEXT:    movk x8, #49186, lsl #48
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fcsel d0, d1, d0, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_fsub_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    adrp x8, .LCPI43_0
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    ldr d0, [x8, :lo12:.LCPI43_0]
+; CHECK-SD-NEXT:    mov x8, #3689348814741910323 // =0x3333333333333333
+; CHECK-SD-NEXT:    movk x8, #49186, lsl #48
+; CHECK-SD-NEXT:    fmov d1, x8
+; CHECK-SD-NEXT:    fcsel d0, d1, d0, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_fsub_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI43_0
+; CHECK-GI-NEXT:    and w9, w0, #0x1
+; CHECK-GI-NEXT:    ldr d0, [x8, :lo12:.LCPI43_0]
+; CHECK-GI-NEXT:    mov x8, #3689348814741910323 // =0x3333333333333333
+; CHECK-GI-NEXT:    tst w9, #0x1
+; CHECK-GI-NEXT:    movk x8, #49186, lsl #48
+; CHECK-GI-NEXT:    fmov d1, x8
+; CHECK-GI-NEXT:    fcsel d0, d1, d0, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fsub double %sel, 5.1
   ret double %bo
 }
 
 define double @fsub_constant_sel_constants(i1 %cond) {
-; CHECK-LABEL: fsub_constant_sel_constants:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI44_0
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI44_0]
-; CHECK-NEXT:    mov x8, #3689348814741910323 // =0x3333333333333333
-; CHECK-NEXT:    movk x8, #16418, lsl #48
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fcsel d0, d1, d0, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: fsub_constant_sel_constants:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    adrp x8, .LCPI44_0
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    ldr d0, [x8, :lo12:.LCPI44_0]
+; CHECK-SD-NEXT:    mov x8, #3689348814741910323 // =0x3333333333333333
+; CHECK-SD-NEXT:    movk x8, #16418, lsl #48
+; CHECK-SD-NEXT:    fmov d1, x8
+; CHECK-SD-NEXT:    fcsel d0, d1, d0, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: fsub_constant_sel_constants:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI44_0
+; CHECK-GI-NEXT:    and w9, w0, #0x1
+; CHECK-GI-NEXT:    ldr d0, [x8, :lo12:.LCPI44_0]
+; CHECK-GI-NEXT:    mov x8, #3689348814741910323 // =0x3333333333333333
+; CHECK-GI-NEXT:    tst w9, #0x1
+; CHECK-GI-NEXT:    movk x8, #16418, lsl #48
+; CHECK-GI-NEXT:    fmov d1, x8
+; CHECK-GI-NEXT:    fcsel d0, d1, d0, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fsub double 5.1, %sel
   ret double %bo
 }
 
 define double @sel_constants_fmul_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_fmul_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI45_0
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI45_0]
-; CHECK-NEXT:    mov x8, #7378697629483820646 // =0x6666666666666666
-; CHECK-NEXT:    movk x8, #49204, lsl #48
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fcsel d0, d1, d0, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_fmul_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    adrp x8, .LCPI45_0
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    ldr d0, [x8, :lo12:.LCPI45_0]
+; CHECK-SD-NEXT:    mov x8, #7378697629483820646 // =0x6666666666666666
+; CHECK-SD-NEXT:    movk x8, #49204, lsl #48
+; CHECK-SD-NEXT:    fmov d1, x8
+; CHECK-SD-NEXT:    fcsel d0, d1, d0, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_fmul_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI45_0
+; CHECK-GI-NEXT:    and w9, w0, #0x1
+; CHECK-GI-NEXT:    ldr d0, [x8, :lo12:.LCPI45_0]
+; CHECK-GI-NEXT:    mov x8, #7378697629483820646 // =0x6666666666666666
+; CHECK-GI-NEXT:    tst w9, #0x1
+; CHECK-GI-NEXT:    movk x8, #49204, lsl #48
+; CHECK-GI-NEXT:    fmov d1, x8
+; CHECK-GI-NEXT:    fcsel d0, d1, d0, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fmul double %sel, 5.1
   ret double %bo
 }
 
 define double @sel_constants_fdiv_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_fdiv_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI46_0
-; CHECK-NEXT:    adrp x9, .LCPI46_1
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI46_0]
-; CHECK-NEXT:    ldr d1, [x9, :lo12:.LCPI46_1]
-; CHECK-NEXT:    fcsel d0, d1, d0, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_fdiv_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    adrp x8, .LCPI46_0
+; CHECK-SD-NEXT:    adrp x9, .LCPI46_1
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    ldr d0, [x8, :lo12:.LCPI46_0]
+; CHECK-SD-NEXT:    ldr d1, [x9, :lo12:.LCPI46_1]
+; CHECK-SD-NEXT:    fcsel d0, d1, d0, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_fdiv_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI46_1
+; CHECK-GI-NEXT:    adrp x9, .LCPI46_0
+; CHECK-GI-NEXT:    ldr d0, [x8, :lo12:.LCPI46_1]
+; CHECK-GI-NEXT:    ldr d1, [x9, :lo12:.LCPI46_0]
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    fcsel d0, d1, d0, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fdiv double %sel, 5.1
   ret double %bo
 }
 
 define double @fdiv_constant_sel_constants(i1 %cond) {
-; CHECK-LABEL: fdiv_constant_sel_constants:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI47_0
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI47_0]
-; CHECK-NEXT:    mov x8, #7378697629483820646 // =0x6666666666666666
-; CHECK-NEXT:    movk x8, #49140, lsl #48
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fcsel d0, d1, d0, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: fdiv_constant_sel_constants:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    adrp x8, .LCPI47_0
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    ldr d0, [x8, :lo12:.LCPI47_0]
+; CHECK-SD-NEXT:    mov x8, #7378697629483820646 // =0x6666666666666666
+; CHECK-SD-NEXT:    movk x8, #49140, lsl #48
+; CHECK-SD-NEXT:    fmov d1, x8
+; CHECK-SD-NEXT:    fcsel d0, d1, d0, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: fdiv_constant_sel_constants:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI47_0
+; CHECK-GI-NEXT:    and w9, w0, #0x1
+; CHECK-GI-NEXT:    ldr d0, [x8, :lo12:.LCPI47_0]
+; CHECK-GI-NEXT:    mov x8, #7378697629483820646 // =0x6666666666666666
+; CHECK-GI-NEXT:    tst w9, #0x1
+; CHECK-GI-NEXT:    movk x8, #49140, lsl #48
+; CHECK-GI-NEXT:    fmov d1, x8
+; CHECK-GI-NEXT:    fcsel d0, d1, d0, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = fdiv double 5.1, %sel
   ret double %bo
 }
 
 define double @sel_constants_frem_constant(i1 %cond) {
-; CHECK-LABEL: sel_constants_frem_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI48_0
-; CHECK-NEXT:    fmov d0, #-4.00000000
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI48_0]
-; CHECK-NEXT:    fcsel d0, d0, d1, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_constants_frem_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    adrp x8, .LCPI48_0
+; CHECK-SD-NEXT:    fmov d0, #-4.00000000
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    ldr d1, [x8, :lo12:.LCPI48_0]
+; CHECK-SD-NEXT:    fcsel d0, d0, d1, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_constants_frem_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI48_0
+; CHECK-GI-NEXT:    fmov d0, #-4.00000000
+; CHECK-GI-NEXT:    ldr d1, [x8, :lo12:.LCPI48_0]
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    tst w8, #0x1
+; CHECK-GI-NEXT:    fcsel d0, d0, d1, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = frem double %sel, 5.1
   ret double %bo
 }
 
 define double @frem_constant_sel_constants(i1 %cond) {
-; CHECK-LABEL: frem_constant_sel_constants:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x9, #7378697629483820646 // =0x6666666666666666
-; CHECK-NEXT:    adrp x8, .LCPI49_0
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    movk x9, #16404, lsl #48
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI49_0]
-; CHECK-NEXT:    fmov d1, x9
-; CHECK-NEXT:    fcsel d0, d0, d1, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: frem_constant_sel_constants:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov x9, #7378697629483820646 // =0x6666666666666666
+; CHECK-SD-NEXT:    adrp x8, .LCPI49_0
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    movk x9, #16404, lsl #48
+; CHECK-SD-NEXT:    ldr d0, [x8, :lo12:.LCPI49_0]
+; CHECK-SD-NEXT:    fmov d1, x9
+; CHECK-SD-NEXT:    fcsel d0, d0, d1, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: frem_constant_sel_constants:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    adrp x8, .LCPI49_0
+; CHECK-GI-NEXT:    and w9, w0, #0x1
+; CHECK-GI-NEXT:    ldr d0, [x8, :lo12:.LCPI49_0]
+; CHECK-GI-NEXT:    mov x8, #7378697629483820646 // =0x6666666666666666
+; CHECK-GI-NEXT:    tst w9, #0x1
+; CHECK-GI-NEXT:    movk x8, #16404, lsl #48
+; CHECK-GI-NEXT:    fmov d1, x8
+; CHECK-GI-NEXT:    fcsel d0, d0, d1, ne
+; CHECK-GI-NEXT:    ret
   %sel = select i1 %cond, double -4.0, double 23.3
   %bo = frem double 5.1, %sel
   ret double %bo

diff  --git a/llvm/test/CodeGen/AArch64/select_fmf.ll b/llvm/test/CodeGen/AArch64/select_fmf.ll
index 92d8676ca04be..88f517af65bb6 100644
--- a/llvm/test/CodeGen/AArch64/select_fmf.ll
+++ b/llvm/test/CodeGen/AArch64/select_fmf.ll
@@ -1,38 +1,71 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=arm64-- | FileCheck %s
+; RUN: llc < %s -mtriple=arm64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 ; This test provides fmf coverage for DAG combining of selects
 
 ; select Cond0, (select Cond1, X, Y), Y -> select (and Cond0, Cond1), X, Y
 define float @select_select_fold_select_and(float %w, float %x, float %y, float %z) {
-; CHECK-LABEL: select_select_fold_select_and:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    fminnm s4, s1, s2
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fmaxnm s2, s0, s3
-; CHECK-NEXT:    fmov s1, #0.50000000
-; CHECK-NEXT:    fccmp s4, s0, #4, lt
-; CHECK-NEXT:    fadd s1, s0, s1
-; CHECK-NEXT:    fcsel s2, s2, s0, gt
-; CHECK-NEXT:    fadd s4, s1, s2
-; CHECK-NEXT:    fcmp s4, s1
-; CHECK-NEXT:    b.le .LBB0_2
-; CHECK-NEXT:  // %bb.1: // %if.then.i157.i.i
-; CHECK-NEXT:    fmov s0, #1.00000000
-; CHECK-NEXT:    fadd s0, s2, s0
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB0_2: // %if.end.i159.i.i
-; CHECK-NEXT:    mov w8, #52429 // =0xcccd
-; CHECK-NEXT:    mov w9, #13107 // =0x3333
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    movk w8, #48844, lsl #16
-; CHECK-NEXT:    movk w9, #48819, lsl #16
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fmov s4, w9
-; CHECK-NEXT:    fadd s0, s0, s2
-; CHECK-NEXT:    fadd s2, s3, s4
-; CHECK-NEXT:    fcsel s0, s0, s2, gt
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_select_fold_select_and:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    fminnm s4, s1, s2
+; CHECK-SD-NEXT:    fcmp s1, s2
+; CHECK-SD-NEXT:    fmaxnm s2, s0, s3
+; CHECK-SD-NEXT:    fmov s1, #0.50000000
+; CHECK-SD-NEXT:    fccmp s4, s0, #4, lt
+; CHECK-SD-NEXT:    fadd s1, s0, s1
+; CHECK-SD-NEXT:    fcsel s2, s2, s0, gt
+; CHECK-SD-NEXT:    fadd s4, s1, s2
+; CHECK-SD-NEXT:    fcmp s4, s1
+; CHECK-SD-NEXT:    b.le .LBB0_2
+; CHECK-SD-NEXT:  // %bb.1: // %if.then.i157.i.i
+; CHECK-SD-NEXT:    fmov s0, #1.00000000
+; CHECK-SD-NEXT:    fadd s0, s2, s0
+; CHECK-SD-NEXT:    ret
+; CHECK-SD-NEXT:  .LBB0_2: // %if.end.i159.i.i
+; CHECK-SD-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-SD-NEXT:    mov w9, #13107 // =0x3333
+; CHECK-SD-NEXT:    fcmp s1, #0.0
+; CHECK-SD-NEXT:    movk w8, #48844, lsl #16
+; CHECK-SD-NEXT:    movk w9, #48819, lsl #16
+; CHECK-SD-NEXT:    fmov s2, w8
+; CHECK-SD-NEXT:    fmov s4, w9
+; CHECK-SD-NEXT:    fadd s0, s0, s2
+; CHECK-SD-NEXT:    fadd s2, s3, s4
+; CHECK-SD-NEXT:    fcsel s0, s0, s2, gt
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_select_fold_select_and:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    fcmp s1, s2
+; CHECK-GI-NEXT:    fcsel s4, s1, s2, mi
+; CHECK-GI-NEXT:    fcmp s0, s3
+; CHECK-GI-NEXT:    fcsel s5, s0, s3, gt
+; CHECK-GI-NEXT:    fcmp s1, s2
+; CHECK-GI-NEXT:    fmov s1, #0.50000000
+; CHECK-GI-NEXT:    fcsel s2, s5, s0, mi
+; CHECK-GI-NEXT:    fcmp s4, s0
+; CHECK-GI-NEXT:    fadd s1, s0, s1
+; CHECK-GI-NEXT:    fcsel s2, s2, s0, gt
+; CHECK-GI-NEXT:    fadd s4, s1, s2
+; CHECK-GI-NEXT:    fcmp s4, s1
+; CHECK-GI-NEXT:    b.le .LBB0_2
+; CHECK-GI-NEXT:  // %bb.1: // %if.then.i157.i.i
+; CHECK-GI-NEXT:    fmov s0, #1.00000000
+; CHECK-GI-NEXT:    fadd s0, s2, s0
+; CHECK-GI-NEXT:    ret
+; CHECK-GI-NEXT:  .LBB0_2: // %if.end.i159.i.i
+; CHECK-GI-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-GI-NEXT:    mov w9, #13107 // =0x3333
+; CHECK-GI-NEXT:    fcmp s1, #0.0
+; CHECK-GI-NEXT:    movk w8, #48844, lsl #16
+; CHECK-GI-NEXT:    movk w9, #48819, lsl #16
+; CHECK-GI-NEXT:    fmov s2, w8
+; CHECK-GI-NEXT:    fmov s4, w9
+; CHECK-GI-NEXT:    fadd s0, s0, s2
+; CHECK-GI-NEXT:    fadd s2, s3, s4
+; CHECK-GI-NEXT:    fcsel s0, s0, s2, gt
+; CHECK-GI-NEXT:    ret
   %tmp21 = fcmp fast olt float %x, %y
   %tmp22 = select fast i1 %tmp21, float %x, float %y
   %tmp24 = fcmp fast ogt float %tmp22, %w
@@ -63,34 +96,66 @@ exit:                                     ; preds = %if.end.i159.i.i, %if.then.i
 
 ; select Cond0, X, (select Cond1, X, Y) -> select (or Cond0, Cond1), X, Y
 define float @select_select_fold_select_or(float %w, float %x, float %y, float %z) {
-; CHECK-LABEL: select_select_fold_select_or:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    fminnm s4, s1, s2
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fmaxnm s2, s0, s3
-; CHECK-NEXT:    fmov s1, #0.50000000
-; CHECK-NEXT:    fccmp s4, s0, #0, ge
-; CHECK-NEXT:    fadd s1, s0, s1
-; CHECK-NEXT:    fcsel s2, s0, s2, gt
-; CHECK-NEXT:    fadd s4, s1, s2
-; CHECK-NEXT:    fcmp s4, s1
-; CHECK-NEXT:    b.le .LBB1_2
-; CHECK-NEXT:  // %bb.1: // %if.then.i157.i.i
-; CHECK-NEXT:    fmov s0, #1.00000000
-; CHECK-NEXT:    fadd s0, s2, s0
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB1_2: // %if.end.i159.i.i
-; CHECK-NEXT:    mov w8, #52429 // =0xcccd
-; CHECK-NEXT:    mov w9, #13107 // =0x3333
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    movk w8, #48844, lsl #16
-; CHECK-NEXT:    movk w9, #48819, lsl #16
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fmov s4, w9
-; CHECK-NEXT:    fadd s0, s0, s2
-; CHECK-NEXT:    fadd s2, s3, s4
-; CHECK-NEXT:    fcsel s0, s0, s2, gt
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: select_select_fold_select_or:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    fminnm s4, s1, s2
+; CHECK-SD-NEXT:    fcmp s1, s2
+; CHECK-SD-NEXT:    fmaxnm s2, s0, s3
+; CHECK-SD-NEXT:    fmov s1, #0.50000000
+; CHECK-SD-NEXT:    fccmp s4, s0, #0, ge
+; CHECK-SD-NEXT:    fadd s1, s0, s1
+; CHECK-SD-NEXT:    fcsel s2, s0, s2, gt
+; CHECK-SD-NEXT:    fadd s4, s1, s2
+; CHECK-SD-NEXT:    fcmp s4, s1
+; CHECK-SD-NEXT:    b.le .LBB1_2
+; CHECK-SD-NEXT:  // %bb.1: // %if.then.i157.i.i
+; CHECK-SD-NEXT:    fmov s0, #1.00000000
+; CHECK-SD-NEXT:    fadd s0, s2, s0
+; CHECK-SD-NEXT:    ret
+; CHECK-SD-NEXT:  .LBB1_2: // %if.end.i159.i.i
+; CHECK-SD-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-SD-NEXT:    mov w9, #13107 // =0x3333
+; CHECK-SD-NEXT:    fcmp s1, #0.0
+; CHECK-SD-NEXT:    movk w8, #48844, lsl #16
+; CHECK-SD-NEXT:    movk w9, #48819, lsl #16
+; CHECK-SD-NEXT:    fmov s2, w8
+; CHECK-SD-NEXT:    fmov s4, w9
+; CHECK-SD-NEXT:    fadd s0, s0, s2
+; CHECK-SD-NEXT:    fadd s2, s3, s4
+; CHECK-SD-NEXT:    fcsel s0, s0, s2, gt
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: select_select_fold_select_or:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    fcmp s1, s2
+; CHECK-GI-NEXT:    fcsel s4, s1, s2, mi
+; CHECK-GI-NEXT:    fcmp s0, s3
+; CHECK-GI-NEXT:    fcsel s5, s0, s3, gt
+; CHECK-GI-NEXT:    fcmp s1, s2
+; CHECK-GI-NEXT:    fmov s1, #0.50000000
+; CHECK-GI-NEXT:    fcsel s2, s0, s5, mi
+; CHECK-GI-NEXT:    fcmp s4, s0
+; CHECK-GI-NEXT:    fadd s1, s0, s1
+; CHECK-GI-NEXT:    fcsel s2, s0, s2, gt
+; CHECK-GI-NEXT:    fadd s4, s1, s2
+; CHECK-GI-NEXT:    fcmp s4, s1
+; CHECK-GI-NEXT:    b.le .LBB1_2
+; CHECK-GI-NEXT:  // %bb.1: // %if.then.i157.i.i
+; CHECK-GI-NEXT:    fmov s0, #1.00000000
+; CHECK-GI-NEXT:    fadd s0, s2, s0
+; CHECK-GI-NEXT:    ret
+; CHECK-GI-NEXT:  .LBB1_2: // %if.end.i159.i.i
+; CHECK-GI-NEXT:    mov w8, #52429 // =0xcccd
+; CHECK-GI-NEXT:    mov w9, #13107 // =0x3333
+; CHECK-GI-NEXT:    fcmp s1, #0.0
+; CHECK-GI-NEXT:    movk w8, #48844, lsl #16
+; CHECK-GI-NEXT:    movk w9, #48819, lsl #16
+; CHECK-GI-NEXT:    fmov s2, w8
+; CHECK-GI-NEXT:    fmov s4, w9
+; CHECK-GI-NEXT:    fadd s0, s0, s2
+; CHECK-GI-NEXT:    fadd s2, s3, s4
+; CHECK-GI-NEXT:    fcsel s0, s0, s2, gt
+; CHECK-GI-NEXT:    ret
   %tmp21 = fcmp fast olt float %x, %y
   %tmp22 = select fast i1 %tmp21, float %x, float %y
   %tmp24 = fcmp fast ogt float %tmp22, %w
@@ -118,3 +183,5 @@ exit:                                     ; preds = %if.end.i159.i.i, %if.then.i
   %phi1 = phi float [ %add.i156.i.i, %if.then.i157.i.i ], [ %select3, %if.end.i159.i.i ]
   ret float %phi1
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}

diff  --git a/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll b/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
index 23de2d668cffa..32fc9c1377704 100644
--- a/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
+++ b/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
@@ -1,14 +1,22 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 ; Compare if negative and select of constants where one constant is zero.
 
 define i32 @neg_sel_constants(i32 %a) {
-; CHECK-LABEL: neg_sel_constants:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #5 // =0x5
-; CHECK-NEXT:    and w0, w8, w0, asr #31
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: neg_sel_constants:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #5 // =0x5
+; CHECK-SD-NEXT:    and w0, w8, w0, asr #31
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: neg_sel_constants:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #5 // =0x5
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csel w0, w8, wzr, lt
+; CHECK-GI-NEXT:    ret
   %tmp.1 = icmp slt i32 %a, 0
   %retval = select i1 %tmp.1, i32 5, i32 0
   ret i32 %retval
@@ -17,11 +25,18 @@ define i32 @neg_sel_constants(i32 %a) {
 ; Compare if negative and select of constants where one constant is zero and the other is a single bit.
 
 define i32 @neg_sel_special_constant(i32 %a) {
-; CHECK-LABEL: neg_sel_special_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    lsr w8, w0, #22
-; CHECK-NEXT:    and w0, w8, #0x200
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: neg_sel_special_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    lsr w8, w0, #22
+; CHECK-SD-NEXT:    and w0, w8, #0x200
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: neg_sel_special_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    cset w8, lt
+; CHECK-GI-NEXT:    lsl w0, w8, #9
+; CHECK-GI-NEXT:    ret
   %tmp.1 = icmp slt i32 %a, 0
   %retval = select i1 %tmp.1, i32 512, i32 0
   ret i32 %retval
@@ -30,10 +45,16 @@ define i32 @neg_sel_special_constant(i32 %a) {
 ; Compare if negative and select variable or zero.
 
 define i32 @neg_sel_variable_and_zero(i32 %a, i32 %b) {
-; CHECK-LABEL: neg_sel_variable_and_zero:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    and w0, w1, w0, asr #31
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: neg_sel_variable_and_zero:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    and w0, w1, w0, asr #31
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: neg_sel_variable_and_zero:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csel w0, w1, wzr, lt
+; CHECK-GI-NEXT:    ret
   %tmp.1 = icmp slt i32 %a, 0
   %retval = select i1 %tmp.1, i32 %b, i32 0
   ret i32 %retval
@@ -42,10 +63,16 @@ define i32 @neg_sel_variable_and_zero(i32 %a, i32 %b) {
 ; Compare if not positive and select the same variable as being compared: smin(a, 0).
 
 define i32 @not_pos_sel_same_variable(i32 %a) {
-; CHECK-LABEL: not_pos_sel_same_variable:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    and w0, w0, w0, asr #31
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: not_pos_sel_same_variable:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    and w0, w0, w0, asr #31
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: not_pos_sel_same_variable:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmp w0, #1
+; CHECK-GI-NEXT:    csel w0, w0, wzr, lt
+; CHECK-GI-NEXT:    ret
   %tmp = icmp slt i32 %a, 1
   %min = select i1 %tmp, i32 %a, i32 0
   ret i32 %min
@@ -56,11 +83,18 @@ define i32 @not_pos_sel_same_variable(i32 %a) {
 ; Compare if positive and select of constants where one constant is zero.
 
 define i32 @pos_sel_constants(i32 %a) {
-; CHECK-LABEL: pos_sel_constants:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #5 // =0x5
-; CHECK-NEXT:    bic w0, w8, w0, asr #31
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: pos_sel_constants:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #5 // =0x5
+; CHECK-SD-NEXT:    bic w0, w8, w0, asr #31
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: pos_sel_constants:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    mov w8, #5 // =0x5
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csel w0, w8, wzr, ge
+; CHECK-GI-NEXT:    ret
   %tmp.1 = icmp sgt i32 %a, -1
   %retval = select i1 %tmp.1, i32 5, i32 0
   ret i32 %retval
@@ -69,11 +103,18 @@ define i32 @pos_sel_constants(i32 %a) {
 ; Compare if positive and select of constants where one constant is zero and the other is a single bit.
 
 define i32 @pos_sel_special_constant(i32 %a) {
-; CHECK-LABEL: pos_sel_special_constant:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #512 // =0x200
-; CHECK-NEXT:    bic w0, w8, w0, lsr #22
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: pos_sel_special_constant:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #512 // =0x200
+; CHECK-SD-NEXT:    bic w0, w8, w0, lsr #22
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: pos_sel_special_constant:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    cset w8, ge
+; CHECK-GI-NEXT:    lsl w0, w8, #9
+; CHECK-GI-NEXT:    ret
   %tmp.1 = icmp sgt i32 %a, -1
   %retval = select i1 %tmp.1, i32 512, i32 0
   ret i32 %retval
@@ -82,10 +123,16 @@ define i32 @pos_sel_special_constant(i32 %a) {
 ; Compare if positive and select variable or zero.
 
 define i32 @pos_sel_variable_and_zero(i32 %a, i32 %b) {
-; CHECK-LABEL: pos_sel_variable_and_zero:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    bic w0, w1, w0, asr #31
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: pos_sel_variable_and_zero:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    bic w0, w1, w0, asr #31
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: pos_sel_variable_and_zero:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csel w0, w1, wzr, ge
+; CHECK-GI-NEXT:    ret
   %tmp.1 = icmp sgt i32 %a, -1
   %retval = select i1 %tmp.1, i32 %b, i32 0
   ret i32 %retval
@@ -94,10 +141,16 @@ define i32 @pos_sel_variable_and_zero(i32 %a, i32 %b) {
 ; Compare if not negative or zero and select the same variable as being compared: smax(a, 0).
 
 define i32 @not_neg_sel_same_variable(i32 %a) {
-; CHECK-LABEL: not_neg_sel_same_variable:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    bic w0, w0, w0, asr #31
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: not_neg_sel_same_variable:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    bic w0, w0, w0, asr #31
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: not_neg_sel_same_variable:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    cmp w0, #0
+; CHECK-GI-NEXT:    csel w0, w0, wzr, gt
+; CHECK-GI-NEXT:    ret
   %tmp = icmp sgt i32 %a, 0
   %min = select i1 %tmp, i32 %a, i32 0
   ret i32 %min
@@ -107,11 +160,17 @@ define i32 @not_neg_sel_same_variable(i32 %a) {
 
 ; ret = (x-y) > 0 ? x-y : 0
 define i32 @PR31175(i32 %x, i32 %y) {
-; CHECK-LABEL: PR31175:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    sub w8, w0, w1
-; CHECK-NEXT:    bic w0, w8, w8, asr #31
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: PR31175:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    sub w8, w0, w1
+; CHECK-SD-NEXT:    bic w0, w8, w8, asr #31
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: PR31175:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    subs w8, w0, w1
+; CHECK-GI-NEXT:    csel w0, w8, wzr, gt
+; CHECK-GI-NEXT:    ret
   %sub = sub nsw i32 %x, %y
   %cmp = icmp sgt i32 %sub, 0
   %sel = select i1 %cmp, i32 %sub, i32 0
@@ -119,97 +178,159 @@ define i32 @PR31175(i32 %x, i32 %y) {
 }
 
 define i8 @sel_shift_bool_i8(i1 %t) {
-; CHECK-LABEL: sel_shift_bool_i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-128 // =0xffffff80
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    csel w0, w8, wzr, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_shift_bool_i8:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #-128 // =0xffffff80
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    csel w0, w8, wzr, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_shift_bool_i8:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    lsl w0, w0, #7
+; CHECK-GI-NEXT:    ret
   %shl = select i1 %t, i8 128, i8 0
   ret i8 %shl
 }
 
 define i16 @sel_shift_bool_i16(i1 %t) {
-; CHECK-LABEL: sel_shift_bool_i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #128 // =0x80
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    csel w0, w8, wzr, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_shift_bool_i16:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #128 // =0x80
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    csel w0, w8, wzr, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_shift_bool_i16:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    lsl w0, w8, #7
+; CHECK-GI-NEXT:    ret
   %shl = select i1 %t, i16 128, i16 0
   ret i16 %shl
 }
 
 define i32 @sel_shift_bool_i32(i1 %t) {
-; CHECK-LABEL: sel_shift_bool_i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #64 // =0x40
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    csel w0, w8, wzr, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_shift_bool_i32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #64 // =0x40
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    csel w0, w8, wzr, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_shift_bool_i32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    and w8, w0, #0x1
+; CHECK-GI-NEXT:    lsl w0, w8, #6
+; CHECK-GI-NEXT:    ret
   %shl = select i1 %t, i32 64, i32 0
   ret i32 %shl
 }
 
 define i64 @sel_shift_bool_i64(i1 %t) {
-; CHECK-LABEL: sel_shift_bool_i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #65536 // =0x10000
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    csel x0, x8, xzr, ne
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_shift_bool_i64:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    mov w8, #65536 // =0x10000
+; CHECK-SD-NEXT:    tst w0, #0x1
+; CHECK-SD-NEXT:    csel x0, x8, xzr, ne
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_shift_bool_i64:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-GI-NEXT:    and x8, x0, #0x1
+; CHECK-GI-NEXT:    lsl x0, x8, #16
+; CHECK-GI-NEXT:    ret
   %shl = select i1 %t, i64 65536, i64 0
   ret i64 %shl
 }
 
 define <16 x i8> @sel_shift_bool_v16i8(<16 x i1> %t) {
-; CHECK-LABEL: sel_shift_bool_v16i8:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    shl v0.16b, v0.16b, #7
-; CHECK-NEXT:    movi v1.16b, #128
-; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
-; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_shift_bool_v16i8:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    shl v0.16b, v0.16b, #7
+; CHECK-SD-NEXT:    movi v1.16b, #128
+; CHECK-SD-NEXT:    cmlt v0.16b, v0.16b, #0
+; CHECK-SD-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_shift_bool_v16i8:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    shl v0.16b, v0.16b, #7
+; CHECK-GI-NEXT:    movi v1.16b, #128
+; CHECK-GI-NEXT:    sshr v0.16b, v0.16b, #7
+; CHECK-GI-NEXT:    and v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT:    ret
   %shl = select <16 x i1> %t, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>, <16 x i8> zeroinitializer
   ret <16 x i8> %shl
 }
 
 define <8 x i16> @sel_shift_bool_v8i16(<8 x i1> %t) {
-; CHECK-LABEL: sel_shift_bool_v8i16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
-; CHECK-NEXT:    movi v1.8h, #128
-; CHECK-NEXT:    shl v0.8h, v0.8h, #15
-; CHECK-NEXT:    cmlt v0.8h, v0.8h, #0
-; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_shift_bool_v8i16:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    ushll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT:    movi v1.8h, #128
+; CHECK-SD-NEXT:    shl v0.8h, v0.8h, #15
+; CHECK-SD-NEXT:    cmlt v0.8h, v0.8h, #0
+; CHECK-SD-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_shift_bool_v8i16:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    ushll v0.8h, v0.8b, #0
+; CHECK-GI-NEXT:    movi v1.8h, #128
+; CHECK-GI-NEXT:    shl v0.8h, v0.8h, #15
+; CHECK-GI-NEXT:    sshr v0.8h, v0.8h, #15
+; CHECK-GI-NEXT:    and v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT:    ret
   %shl= select <8 x i1> %t, <8 x i16> <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>, <8 x i16> zeroinitializer
   ret <8 x i16> %shl
 }
 
 define <4 x i32> @sel_shift_bool_v4i32(<4 x i1> %t) {
-; CHECK-LABEL: sel_shift_bool_v4i32:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
-; CHECK-NEXT:    movi v1.4s, #64
-; CHECK-NEXT:    shl v0.4s, v0.4s, #31
-; CHECK-NEXT:    cmlt v0.4s, v0.4s, #0
-; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_shift_bool_v4i32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT:    movi v1.4s, #64
+; CHECK-SD-NEXT:    shl v0.4s, v0.4s, #31
+; CHECK-SD-NEXT:    cmlt v0.4s, v0.4s, #0
+; CHECK-SD-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_shift_bool_v4i32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-GI-NEXT:    movi v1.4s, #64
+; CHECK-GI-NEXT:    shl v0.4s, v0.4s, #31
+; CHECK-GI-NEXT:    sshr v0.4s, v0.4s, #31
+; CHECK-GI-NEXT:    and v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT:    ret
   %shl = select <4 x i1> %t, <4 x i32> <i32 64, i32 64, i32 64, i32 64>, <4 x i32> zeroinitializer
   ret <4 x i32> %shl
 }
 
 define <2 x i64> @sel_shift_bool_v2i64(<2 x i1> %t) {
-; CHECK-LABEL: sel_shift_bool_v2i64:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    ushll v0.2d, v0.2s, #0
-; CHECK-NEXT:    mov w8, #65536 // =0x10000
-; CHECK-NEXT:    dup v1.2d, x8
-; CHECK-NEXT:    shl v0.2d, v0.2d, #63
-; CHECK-NEXT:    cmlt v0.2d, v0.2d, #0
-; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: sel_shift_bool_v2i64:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    ushll v0.2d, v0.2s, #0
+; CHECK-SD-NEXT:    mov w8, #65536 // =0x10000
+; CHECK-SD-NEXT:    dup v1.2d, x8
+; CHECK-SD-NEXT:    shl v0.2d, v0.2d, #63
+; CHECK-SD-NEXT:    cmlt v0.2d, v0.2d, #0
+; CHECK-SD-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: sel_shift_bool_v2i64:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    ushll v0.2d, v0.2s, #0
+; CHECK-GI-NEXT:    adrp x8, .LCPI16_0
+; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI16_0]
+; CHECK-GI-NEXT:    shl v0.2d, v0.2d, #63
+; CHECK-GI-NEXT:    sshr v0.2d, v0.2d, #63
+; CHECK-GI-NEXT:    and v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT:    ret
   %shl = select <2 x i1> %t, <2 x i64> <i64 65536, i64 65536>, <2 x i64> zeroinitializer
   ret <2 x i64> %shl
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}


        


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