[llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)

[David Green via llvm-commits]

================
@@ -35,6 +35,48 @@ static MCInst loadImmediate(MCRegister Reg, unsigned RegBitWidth,
       .addImm(Value.getZExtValue());
 }
 
+static MCInst loadZPRImmediate(MCRegister Reg, unsigned RegBitWidth,
+                               const APInt &Value) {
+  if (Value.getBitWidth() > RegBitWidth)
+    llvm_unreachable("Value must fit in the ZPR Register");
+  // For ZPR, we typically use DUPM instruction to load immediate values
+  return MCInstBuilder(AArch64::DUPM_ZI)
+      .addReg(Reg)
+      .addImm(Value.getZExtValue());
+}
+
+static MCInst loadPPRImmediate(MCRegister Reg, unsigned RegBitWidth,
+                               const APInt &Value) {
+  if (Value.getBitWidth() > RegBitWidth)
+    llvm_unreachable("Value must fit in the PPR Register");
+  // For PPR, we typically use PTRUE instruction to set predicate registers
+  return MCInstBuilder(AArch64::PTRUE_B)
+      .addReg(Reg)
+      .addImm(31); // All lanes true
+}
+
+// Generates instruction to load an FP immediate value into a register.
+static unsigned getLoadFPImmediateOpcode(unsigned RegBitWidth) {
+  switch (RegBitWidth) {
+  case 64:
+    return AArch64::FMOVDi; 
+  case 128:
+    return AArch64::MOVIv2d_ns;
+  }
+  llvm_unreachable("Invalid Value Width");
+}
+
+
+// Generates instruction to load an FP immediate value into a register.
+static MCInst loadFPImmediate(MCRegister Reg, unsigned RegBitWidth,
+                            const APInt &Value) {
+  if (Value.getBitWidth() > RegBitWidth)
+    llvm_unreachable("Value must fit in the FP Register");
+  return MCInstBuilder(getLoadFPImmediateOpcode(RegBitWidth))
----------------
davemgreen wrote:

> Yes, Its a warning but the results may be affected for some instruction due to "live-in values" of register.

Yeah sounds good to fix. I was just surprised to read "llvm-exegesis throws error". It makes it sound like it has never been able to work, but it was just warning.

> Yes, Will add support for ADDXrr in next couple of weeks/months.

ADDXrr is a psuedo, so I wouldn't expect it to work (unless it was expanded?). The test should probably be testing ADDXri, ADDXrs and ADDXrx, as those are the real instructions. It means that the tests have never worked on AArch64 with llvm-exegesis enabled, which would be good to fix just for the sake of having clean tests.

> Added assert for value being range for the generated instructions.

Sounds like a good idea, but where was it added?

> Value (passed to setRegTo()) is zero in practice.

Zero is possibly the worst value for value-prediction, but that at least makes things simpler! Thanks for checking.

> And the PTRUE instruction used to set predicate register ensure all the bits are set to one.

Yeah having an all-off mask doesn't sound very useful. All-on is probably the best idea.

https://github.com/llvm/llvm-project/pull/127564