[llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)
Aiden Grossman via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 20 12:41:10 PST 2025
================
@@ -28,31 +28,28 @@ static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
// Generates instruction to load an immediate value into a register.
static MCInst loadImmediate(MCRegister Reg, unsigned RegBitWidth,
const APInt &Value) {
- if (Value.getBitWidth() > RegBitWidth)
- llvm_unreachable("Value must fit in the Register");
+ assert(Value.getBitWidth() <= RegBitWidth && "Value must fit in the Register");
return MCInstBuilder(getLoadImmediateOpcode(RegBitWidth))
.addReg(Reg)
.addImm(Value.getZExtValue());
}
static MCInst loadZPRImmediate(MCRegister Reg, unsigned RegBitWidth,
const APInt &Value) {
- if (Value.getBitWidth() > RegBitWidth)
- llvm_unreachable("Value must fit in the ZPR Register");
+ assert(Value.getBitWidth() <= RegBitWidth && "Value must fit in the PPR Register");
// For ZPR, we typically use DUPM instruction to load immediate values
return MCInstBuilder(AArch64::DUPM_ZI)
.addReg(Reg)
- .addImm(Value.getZExtValue());
+ .addImm(0x1);
----------------
boomanaiden154 wrote:
Why are we using a constant here rather than what the register value is set to?
https://github.com/llvm/llvm-project/pull/127564
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