[llvm] Introducing a new ISD::POISON SDNode to represent the poison value in the IR. (PR #125883)

[zhijian lin via llvm-commits]

================
@@ -977,6 +977,11 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
   TargetLowering::LegalizeAction Action = TargetLowering::Legal;
   bool SimpleFinishLegalizing = true;
   switch (Node->getOpcode()) {
+  case ISD::POISON: {
+    SDValue UndefNode = DAG.getUNDEF(Node->getValueType(0));
+    ReplaceNode(Node, UndefNode.getNode());
+    break;
+  }
----------------
diggerlin wrote:

I agree. But if I do not add the code here, there are about 26 test cases fail , for example , the test case llvm/test/CodeGen/PowerPC/vec_shuffle.ll

it will use the code in the llvm/lib/Target/PowerPC/PPCInstrAltivec.td

```
def VSPLTB : VXForm_1<524, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
                      "vspltb $VD, $VB, $VA", IIC_VecPerm,
                      [(set v16i8:$VD,
                        (vspltb_shuffle:$VA v16i8:$VB, (undef)))]>;
```

to do a instruction selection.

if I add following definition in the td file for  instruction selection.

```
def VSPLTB : VXForm_1<524, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
                      "vspltb $VD, $VB, $VA", IIC_VecPerm,
                      [(set v16i8:$VD,
                        (vspltb_shuffle:$VA v16i8:$VB, (poison)))]>;
```
                        
  there will a compile error since tablegen do not support poison.
  
  if you `grep "undef"  llvm/lib/Target/*/*.td `
  you will find , there is a lot of place have the same situation. 
  
  and  we need to add tablegen to support `poison` in the patch, I think the patch will be too big. 
  
Can we just add some TODO information before the following code to express your concern?
  
```
  case ISD::POISON: {
    SDValue UndefNode = DAG.getUNDEF(Node->getValueType(0));
    ReplaceNode(Node, UndefNode.getNode());
    break;
  }
```

@Matt Arsenault
  
  

https://github.com/llvm/llvm-project/pull/125883