[llvm] [NVPTX] Remove redundant addressing mode instrs (PR #128044)

[Alex MacLean via llvm-commits]

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@@ -1344,8 +1264,10 @@ bool NVPTXDAGToDAGISel::tryLDGLDU(SDNode *N) {
       return false;
     SDValue Ops[] = { Addr, Chain };
     LD = CurDAG->getMachineNode(*Opcode, DL, InstVTList, Ops);
-  } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
-                          : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
+  } else {
+    TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
+                 : SelectADDRri(Op1.getNode(), Op1, Base, Offset);
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AlexMaclean wrote:

No, Base and Offset are references which these functions will place the correct values into in order to return them.

https://github.com/llvm/llvm-project/pull/128044