[llvm] [NVPTX] Remove redundant addressing mode instrs (PR #128044)

[Artem Belevich via llvm-commits]

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@@ -1344,8 +1264,10 @@ bool NVPTXDAGToDAGISel::tryLDGLDU(SDNode *N) {
       return false;
     SDValue Ops[] = { Addr, Chain };
     LD = CurDAG->getMachineNode(*Opcode, DL, InstVTList, Ops);
-  } else if (TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
-                          : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
+  } else {
+    TM.is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
+                 : SelectADDRri(Op1.getNode(), Op1, Base, Offset);
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Artem-B wrote:

That used to be the condition for `if` but does not do much now.
Did you intend to make it an assertion?

https://github.com/llvm/llvm-project/pull/128044