[llvm] [AMDGPU] Add support for point sample accel out of order returns (PR #127991)

[Jay Foad via llvm-commits]

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@@ -924,8 +951,13 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
           // defs. That's required for a sane index into `VgprMemTypes` below
           assert(TRI->isVectorRegister(*MRI, Op.getReg()));
           VmemType V = getVmemType(Inst);
+          unsigned char TypesMask = 1 << V;
+          // If instruction can have Point Sample Accel applied, we have to flag
+          // this with another potential dependency
+          if (hasPointSampleAccel(Inst))
+            TypesMask |= 1 << VMEM_NOSAMPLER;
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jayfoad wrote:

I think this patch is probably fine as-is. My only hesitation is whether it would be better to do some more refactoring, and fold this logic into `getVmemType` itself, calling it `getVmemTypes` and returning a bit mask. That would force every user of `getVmemType` to consider what to do if more than one bit is set in the mask.

https://github.com/llvm/llvm-project/pull/127991