[llvm] AMDGPU: Restrict src0 to VGPRs only for certain cvt scale opcodes. (PR #127464)

[Joe Nash via llvm-commits]

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@@ -1803,9 +1803,21 @@ class getVOP3SrcForVT<ValueType VT, bit IsTrue16 = 0> {
         1                  : VSrc_b32);
 }
 
+// VGPR only VOP3 src with 9 bit encoding
+class getVOP3VRegSrcForVT<ValueType VT> {
+  RegisterOperand ret = !cond(!eq(VT.Size, 1024) : VRegSrc_1024,
+                              !eq(VT.Size, 512)  : VRegSrc_512,
+                              !eq(VT.Size, 256)  : VRegSrc_256,
+                              !eq(VT.Size, 192)  : VRegSrc_192,
+                              !eq(VT.Size, 128)  : VRegSrc_128,
+                              !eq(VT.Size, 96)   : VRegSrc_96,
+                              !eq(VT.Size, 64)   : VRegSrc_64,
+                              1 : VRegSrc_32);
+}
+
 // Returns the vreg register class to use for sources of VOP3 instructions for the
 // given VT.
-class getVOP3VRegSrcForVT<ValueType VT, bit IsTrue16 = 0, bit IsFake16 = 0> {
+class getVOP3VRegForVT<ValueType VT, bit IsTrue16 = 0, bit IsFake16 = 0> {
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Sisyph wrote:

I think this class is only used VOP_MAC. Can you move it next to that in the VOP2Instructions.td file. That is a a special instruction, and it makes sense we need a special case for it, but I don't want any other uses of  the new getVOP3VRegForVT to appear.

https://github.com/llvm/llvm-project/pull/127464