[llvm] [AMDGPU][MachineRegisterInfo] Extend the MRI live-ins check to account for Subreg (PR #126926)

[Vikash Gupta via llvm-commits]

vg0204 wrote:

> > SILowerSGPRSpill, where KILL flag is introduced based on MRI live-in list.
> 
> Can this look at the block live ins instead?

block live hold T(physReg+LaneBitmask) as liveIns, so its check is meant to handle only liveIns existing as T, while in SILowerSGPR needs check for CSR physReg used i.e. dword-sized reg as liveIn. So, straight direct check without anything additional not seems possible. With MRI, it holds only the entire live PhysReg as MCRegister in its list, so just its extension by my patch does the job. 

https://github.com/llvm/llvm-project/pull/126926