[llvm] [LV] Regen a couple of tests with UTC (PR #127785)

[Florian Hahn via llvm-commits]

================
@@ -1,21 +1,334 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
 ; RUN: opt < %s -passes=loop-vectorize -S | FileCheck %s
 
-; CHECK: fadd
-; CHECK-NEXT: fadd
-; CHECK-NEXT: fadd
-; CHECK-NEXT: fadd
-; CHECK-NEXT: fadd
-; CHECK-NEXT: fadd
-; CHECK-NEXT: fadd
-; CHECK-NEXT: fadd
-; CHECK-NEXT: =
-; CHECK-NOT: fadd
-; CHECK-SAME: >
-
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-ibm-linux-gnu"
 
-define void @QLA_F3_r_veq_norm2_V(ptr noalias nocapture %r, ptr noalias nocapture readonly %a, i32 signext %n) #0 {
+define void @QLA_F3_r_veq_norm2_V(ptr noalias %r, ptr noalias %a, i32 %n) {
----------------
fhahn wrote:

Could you add a brief comment that here we expect the loop with double reductions to be interleaved 8 times to make it easier to see what this checks now? Same for small-loop-rdx.

https://github.com/llvm/llvm-project/pull/127785